SCR controlled by the power bias

Abstract

A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.

1. An SCR, defining a trigger voltage, functionally connected between a first node to be protected and a second node, the SCR comprising:
 a PNP transistor with its emitter functionally connected to the first node; 
 a first resistor coupling the base of the PNP transistor to a voltage source; 
 an NPN transistor with its collector functionally connected to the base of the PNP transistor, its base connected to the collector of the PNP transistor, and its emitter functionally connected to the second node, wherein the PNP and NPN comprise the protective SCR, and wherein the voltage source biases the base of the PNP transistor and thereby controls the trigger voltage of the SCR. 
 
     
     
       2. The SCR, demonstrating a holding current, of  claim 1  further comprising:
 a second resistor connecting the base to the emitter of the NPN transistor that determines the holding current. 
 
     
     
       3. The SCR of  claim 1  further comprising:
 a second PNP transistor with its emitter connected to the power source, its base to the base of the PNP transistor, and its collector to the base of the NPN transistor, wherein the second PNP and the NPN transistors constitute a second SCR, wherein the second SCR protects the power source node. 
 
     
     
       4. The SCR of  claim 3  further comprising a third resistor arranged one series with the first resistor, the third resistor connecting to the power source node, and wherein the second PNP transistor is connected to the junction of the resistor and the third resistor. 
     
     
       5. The SCR of  claim 4  further comprising a fourth resistor connecting the base to the emitter of the NPN transistor that determines the holding current of both SCRs. 
     
     
       6. A dual SCR, the dual SCR arranged functionally to protect both a voltage source and a first node, and a second node, the dual SCR defining a first trigger voltage for the first node and a second trigger voltage for the voltage source, the dual SCR comprising:
 a PNP transistor with its emitter functionally connected to the first node; 
 a first resistor coupling the base of the PNP transistor to the voltage source; 
 a first NPN transistor with its collector functionally connected to the base of the PNP transistor, its base functionally connected to the collector of the PNP transistor, and its emitter functionally connected to the second node; 
 a second PNP transistor with its emitter functionally connected to the voltage source, its collector functionally connected to the base of the NPN transistor, and its base functionally connected to the collector of the NPN transistor, wherein the voltage source biases the trigger voltage of the first node. 
 
     
     
       7. The dual SCR of  claim 6  wherein the first PNP and the first NPN define a circuit that triggers when the first node reaches the first trigger voltage, and wherein the second PNP and the first NPN define a second trigger circuit that triggers when the voltage source reaches the second trigger voltage. 
     
     
       8. A protective SCR functionally connected between a node to be protected and a second node, the SCR comprising:
 an N well and a P well overlaying an N buried layer, 
 a first N+ tub and a first P+ tub formed in the N well; the first N+ tub coupled to a node connecting to a power source; the P+ tub functionally connecting to the node to be protected; 
 a second N+ tub and P+ tub formed in the P well; the second N+ tub functionally connected to the second node, 
 
       a resistor that functionally connects the second P+ tub to the second node;
 the first P+ tub, the first N+ tub and N buried layer, and the P well forming a bipolar PNP transistor, 
 the N well, the P well and the second N+ tub forming a bipolar NPN transistor, wherein functionally the collector of the bipolar PNP connects to the base of bipolar NPN, and functionally the base of the bipolar NPN connects to the collector of the bipolar NPN, the bipolar PNP and NPN arrange in a regenerative latching configuration; and wherein the power source controls the voltage level on the node to be protected that triggers the regenerative latching of the bipolar NPN and PNP. 
 
     
     
       9. The protective SCR of  claim 8  further comprising a low doped N well formed around the first N+ tub and a low doped P well formed around the first P+ tub, the low doped wells arrange to increase the breakdown voltage between the node to be protected and the node functionally connected to the power source, the breakdown voltage of the base to emitter of the bipolar PNP.