Counter and Frequency divider thereof

Abstract

A frequency divider includes a transmission gate, a first inverter, a first switch circuit, a second switch circuit, and a second inverter. The transmission gate transmits a clock signal according to an inverted enable signal. The first inverter inverts the clock signal outputted from the transmission gate. The first switch circuit generates a first control signal according to the inverted clock signal and an output signal of the frequency divider. The second switch circuit generates a second control signal according to the clock signal, the inverted clock signal, and the first control signal. The second inverter inverts the second control signal to generate the output signal. The frequency of the clock signal is a multiple of the frequency of the output signal.

1. A frequency divider, comprising:
 a transmission gate transmitting a clock signal according to an inverted enable signal; 
 a first inverter inverting the clock signal outputted from the transmission gate; 
 a first switch circuit generating a first control signal according to the inverted clock signal and an output signal of the frequency divider; 
 a second switch circuit generating a second control signal according to the clock signal, the inverted clock signal, and the first control signal, wherein the second switch circuit comprises: 
 a first transistor having a gate, a source, and a drain, wherein the source of the first transistor receives a supply voltage; 
 a fourth transistor having a gate, a source, and a drain, wherein drain of the fourth transistor is connected to a ground terminal, and the gates of the first transistor and the fourth transistor receive the first control signal from the first switch circuit; 
 a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor receives the clock signal, and the source of the second transistor is connected to the drain of the first transistor; and 
 a third transistor having a gate, a source, and a drain, wherein the gate of the third transistor receives the inverted clock signal, the drain of third transistor, connected to the drain of the second transistor, outputs the second control signal, and the source of the third transistor is connected to the source of the fourth transistor; and 
 a second inverter inverting the second control signal to generate the output signal, 
 wherein the frequency of the clock signal is a multiple of the frequency of the output signal. 
 
     
     
       2. The frequency divider as claimed in  claim 1 , wherein the first transistor, the second transistor, and the forth transistor are P channel field effect transistors. 
     
     
       3. The frequency divider as claimed in  claim 2 , wherein the third transistor is N channel field effect transistors. 
     
     
       4. The frequency divider as claimed in  claim 1 , wherein the first switch circuit comprises:
 a fifth transistor having a gate, a source, and a drain, wherein the source of the first transistor receives the supply voltage; 
 an eighth transistor having a gate, a source, and a drain, wherein drain of the eighth transistor is connected to the ground terminal, and the gates of the fifth transistor and the eighth transistor receive the output signal of the frequency divider; 
 a sixth transistor having a gate, a source, and a drain, wherein the gate of the sixth transistor receives the inverted clock signal, and the source of the sixth transistor is connected to the drain of the fifth transistor; and 
 a seventh transistor having a gate, a source, and a drain, wherein the gate of the seventh transistor receives the clock signal, the source of seventh transistor, outputting the first control signal, is connected to the drain of the sixth transistor, and the drain of the seventh transistor is connected to the source of the eighth transistor. 
 
     
     
       5. The frequency divider as claimed in  claim 4 , wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are the P channel field effect transistors. 
     
     
       6. The frequency divider as claimed in  claim 1 , further comprising a ninth transistor connected to the a output terminal of the transmission gate, wherein the ninth transistor discharges the output terminal to a logic low level according to the inverted enable signal. 
     
     
       7. The frequency divider as claimed in  claim 1 , further comprising a first capacitor, connected to the drain of the second transistor, for maintaining a voltage value of the second control signal. 
     
     
       8. The frequency divider as claimed in  claim 1 , further comprising a second capacitor, connected to the drain of the sixth transistor, for maintaining a voltage value of the first control signal. 
     
     
       9. A counter, comprising:
 a plurality of frequency dividers connected in series, each of the frequency dividers comprising:
 a transmission gate transmitting a clock signal according to an inverted enable signal; 
 a first inverter inverting the clock signal outputted from the transmission gate; 
 a first switch circuit generating a first control signal according to the inverted clock signal and an output signal of the frequency divider; 
 a second switch circuit generating a second control signal according to the clock signal, the inverted clock signal, and the first control signal, wherein the second switch circuit comprises: 
 a first transistor having a gate, a source, and a drain, wherein the source of the first transistor receives a supply voltage; 
 a fourth transistor having a gate, a source, and a drain, wherein drain of the fourth transistor is connected to a ground terminal, and the gates of the first transistor and the fourth transistor receive the first control signal from the first switch circuit; 
 a second transistor having a gate, a source, and a drain, wherein the gate of the second transistor receives the clock signal, and the source of the second transistor is connected to the drain of the first transistor; and 
 a third transistor having a gate, a source, and a drain, wherein the gate of the third transistor receives the inverted clock signal, the drain of third transistor, connected to the drain of the second transistor, outputs the second control signal, and the source of the third transistor is connected to the source of the fourth transistor; and 
 a second inverter inverting the second control signal to generate the output signal, whereby the frequency of the clock signal is a multiple of the frequency of the output signal. 
 
 
     
     
       10. The counter as claimed in  claim 9 , wherein the frequency of the output signal is equal to the frequency of the clock signal divided by 2 N , in which N is the number of the frequency dividers. 
     
     
       11. The counter as claimed in  claim 9 , wherein the output signal of previous frequency divider is inputted as the clock signal of the next frequency divider. 
     
     
       12. The counter as claimed in  claim 9 , wherein the first switch circuit comprises:
 a fifth transistor having a gate, a source, and a drain, wherein the source of the fifth transistor receives the supply voltage; 
 an eighth transistor having a gate, a source, and a drain, wherein drain of the eighth transistor is connected to the ground terminal, and the gates of the fifth transistor and the eighth transistor receive the output signal of the frequency divider; 
 a sixth transistor having a gate, a source, and a drain, wherein the gate of the sixth transistor receives the inverted clock signal, and the source of the sixth transistor is connected to the drain of the fifth transistor; and 
 a seventh transistor having a gate, a source, and a drain, wherein the gate of the seventh transistor receives the clock signal, the source of seventh transistor, outputting the first control signal, is connected to the source of the sixth transistor, and the drain of the seventh transistor is connected to the source of the eighth transistor.