DLL circuit

Abstract

A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.

1. A DLL circuit comprising:
 a first delay circuit delaying a first signal by a first delay time, thus producing a third signal; and 
 a second delay circuit delaying the first signal by a second delay time, thus producing a fourth signal, 
 wherein the third signal differs from the fourth signal by a single delay stage. 
 
     
     
       2. The DLL circuit according to  claim 1 , wherein both the first delay circuit and the second delay circuit include a same number of delay elements. 
     
     
       3. The DLL circuit according to  claim 2 , wherein each of the delay elements includes a plurality of MOS transistors, and wherein a gate length of the MOS transistor included in the first delay circuit differs from a gate length of the MOS transistor included in the second delay circuit. 
     
     
       4. The DLL circuit according to  claim 2 , wherein each of the delay elements includes a plurality of MOS transistors, and wherein a gate width of the MOS transistor included in the first delay circuit differs from a gate width of the MOS transistor included in the second delay circuit. 
     
     
       5. The DLL circuit according to  claim 1 , wherein the first delay circuit receiving a second signal delays the first signal or the second signal by the first delay time so as to produce the third signal, and wherein the second delay circuit receiving the second signal delays the first signal or the second signal by the second delay time so as to produce the fourth signal. 
     
     
       6. The DLL circuit according to  claim 5 , wherein the first signal and the second signal is switched over in response to a first control signal supplied each of the first delay circuit and the second delay circuit so that the third signal and the fourth signals are produced based on either the first signal or the second signal selectively. 
     
     
       7. A circuit comprising:
 a first delay circuit that delays a local clock so as to generate a first delayed clock signal, wherein the first delay circuit includes a plurality of first delay elements; and 
 a second delay circuit that delays the local clock so as to generate a second delayed clock signal, wherein the second delay circuit includes a plurality of second delay elements, the number of which is equal to the number of the first delay elements, 
 wherein a difference between the first delayed clock signal and the second delayed clock signal is substantially equal to a delay time corresponding to a stage of the first delay elements. 
 
     
     
       8. The circuit according to  claim 7  further comprising a fine delay circuit and a delay control circuit, wherein the fine delay circuit receiving the first delayed clock signal and the second delayed clock signal generates an internal clock signal by use of the first delayed clock signal and the second delayed clock signal, and wherein the delay control circuit controls the fine delay circuit so as to synchronize the internal clock signal with a reference clock signal. 
     
     
       9. The circuit according to  claim 7 , wherein the first delay element includes at least one first MOS transistor, and wherein the second delay element includes at least one second MOS transistor. 
     
     
       10. The circuit according to  claim 9 , wherein the first MOS transistor differs from the second MOS transistor in terms of a gate length. 
     
     
       11. The circuit according to  claim 9 , wherein the first MOS transistor differs from the second MOS transistor in terms of a gate width.