Flash memory device and method of manufacturing the same

Abstract

Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width. The flash memory device may include a first polysilicon pattern and a second polysilicon pattern on and/or over the tunnel oxide layer and a dielectric pattern on and/or over the tunnel oxide layer, where the first and second polysilicon patterns may be provided. It may also include a third polysilicon pattern on and/or over the dielectric pattern, the third polysilicon pattern having a second width, and a spacer formed on and/or over sidewalls of the first, second and third polysilicon patterns, the dielectric pattern and the tunnel oxide pattern. According to embodiments, the second width may be greater than the first width.

1. A device comprising: a tunnel oxide layer having a first width over a semiconductor substrate, the semiconductor substrate including source and drain regions; a first polysilicon pattern and a second polysilicon pattern over the tunnel oxide layer; a dielectric pattern over the tunnel oxide layer and the first and second polysilicon patterns; and a third polysilicon pattern over the dielectric pattern, the third polysilicon pattern having a second width, wherein the second width is greater than the first width, wherein the tunnel oxide layer is formed only over a channel region of the substrate, and wherein there is only one tunnel oxide layer for the first polysilicon pattern, the second polysilicon pattern, and the third polysilicon pattern. 
     
     
       2. The device of  claim 1 , further comprising a spacer formed over sidewalls of the first, second, and third polysilicon patterns, the dielectric pattern, and the tunnel oxide layer. 
     
     
       3. The device of  claim 1 , wherein a width of the dielectric pattern is substantially the same as the second width of the third polysilicon pattern. 
     
     
       4. The device of  claim 1 , wherein the second width is greater than the first width by approximately 10-20 nm. 
     
     
       5. The device of  claim 1 , wherein the dielectric pattern contacts the tunnel oxide layer between the first polysilicon pattern and the second polysilicon pattern. 
     
     
       6. The device of  claim 1 , wherein a bias provided to the first polysilicon pattern and second polysilicon pattern is substantially identical to a bias provided to the third polysilicon pattern. 
     
     
       7. A device comprising; a tunnel oxide layer having a first width over a semiconductor substrate; a floating gate formed over the tunnel oxide layer; and a control gate formed over the floating gate, wherein a pattern for the floating gate has a first width and a pattern for the control gate has a second width, the second width being greater than the first width, wherein the tunnel oxide layer is formed only over a channel region of the substrate, and wherein there is only one tunnel oxide layer for the patterns for the floating gate and the control gate. 
     
     
       8. The device of  claim 7 , comprising:
 a dielectric pattern over the tunnel oxide layer. 
 
     
     
       9. The device of  claim 8 , further comprising a spacer formed over sidewalls of the floating gate, the control gate, the dielectric pattern, and the tunnel oxide layer. 
     
     
       10. The device of  claim 8 , wherein the second width is greater than the first width by approximately 10-20 nm. 
     
     
       11. The device of  claim 10 , wherein a bias provided to the floating gate and the control gate is substantially identical.