Apparatus and method for dynamic circuit element selection in an digital-to-analog converter

Abstract

According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

1. An apparatus, comprising:
 a first circuit to receive input data and provide a plurality of first signals asserted based on the input data; 
 a second circuit to receive the plurality of first signals and provide a plurality of second signals used to select a plurality of circuit elements; and 
 a third circuit to generate a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit, wherein the third circuit comprises:
 a register to store a current value of the control; 
 a data controller to receive the input data and to provide control data; and 
 a summer to receive and sum the control data from the data controller and a current value of the control from the register, and to provide a new value of the control to the register. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the fractional data weight is a value between zero and the value of the input data, inclusive. 
     
     
       3. The apparatus of  claim 2 , wherein the fractional data weight is rounded up or down to the nearest whole number. 
     
     
       4. The apparatus of  claim 3 , wherein the fractional data weight is one-half of the input data rounded up or down to the nearest whole number. 
     
     
       5. The apparatus of  claim 1 , wherein the plurality of second signals selects the plurality of circuit elements in a sequential order. 
     
     
       6. The apparatus of  claim 1 , wherein the first circuit asserts a number of first signals based on the input data, and wherein the number of second signals asserted is equal to the number of first signals asserted. 
     
     
       7. The apparatus of  claim 1 , wherein the first circuit is configured to perform thermometer decoding on the input data and configured to provide thermometer decoded signals as the plurality of first signals. 
     
     
       8. The apparatus of  claim 1 , wherein the second circuit includes a plurality of multiplexers, each multiplexer configured to receive the plurality of first signals in a different order and configured to provide one of the plurality of second signals. 
     
     
       9. The apparatus of  claim 8 , wherein the plurality of multiplexers are configured to receive the control from the third circuit and to provide the plurality of first signals, circularly rotated by an amount determined by the control, as the plurality of second signals. 
     
     
       10. The apparatus of  claim 9 , wherein the plurality of first signals are circularly rotated by an amount equal to the value of the fractional data weight of the input data. 
     
     
       11. The apparatus of  claim 1 , wherein the control data is the fractional data weight of the input data. 
     
     
       12. The apparatus of  claim 1 , wherein the data controller further provides a carry-in to the summer to control rounding of the control data, and the summer is configured to sum the control data, the current value of the control, and the carry-in to provide the new value of the control to the register. 
     
     
       13. The apparatus of  claim 12 , wherein the data controller includes:
 a first logic device configured to generate the carry-in value as a ‘0’ or the first bit of the input data based on a mode select signal indicating a desired rounding mode; 
 a second logic device configured to generate a first bit of the control data as the second bit of the input data; 
 a third logic device configured to generate a second bit of the control data as the third bit of the input data; and 
 a fourth logic device configured to generate a third bit of the control data as a ‘0’. 
 
     
     
       14. The apparatus of  claim 13 , wherein the first through fourth logic devices are multiplexers. 
     
     
       15. An integrated circuit, comprising:
 a first circuit to receive input data and provide a plurality of first signals asserted based on the input data; 
 a second circuit to receive the plurality of first signals and provide a plurality of second signals used to select a plurality of circuit elements; and 
 a third circuit to generate a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit, wherein the third circuit comprises:
 a register to store a current value of the control; 
 a data controller to receive the input data and to provide control data; and 
 a summer to receive and to sum the control data from the data controller and a current value of the control from the register, and to provide a new value of the control to the register, wherein the control data is the fractional data weight of the input data. 
 
 
     
     
       16. The integrated circuit of  claim 15 , wherein the fractional data weight is a value between zero and the value of the input data, inclusive, rounded up or down to the nearest whole number. 
     
     
       17. The integrated circuit of  claim 15 , wherein the first circuit is configured to perform thermometer decoding on the input data and provides thermometer decoded signals as the plurality of first signals. 
     
     
       18. The integrated circuit of  claim 15 , wherein the second circuit further comprises:
 a plurality of multiplexers to receive the control from the third circuit and to provide the plurality of first signals, circularly rotated by an amount equal to the value of the fractional data weight of the input data, as the plurality of second signals. 
 
     
     
       19. The integrated circuit of  claim 15 , wherein the data controller is further configured to provide a carry-in to the summer to control rounding of the control data, and the summer sums the control data, the current value of the control, and the carry-in to provide the new value of the control to the register. 
     
     
       20. A method, comprising:
 asserting zero or more of a plurality of first signals based on input data; 
 generating a control using a fractional data weight of the input data; 
 mapping the plurality of first signals to a plurality of second signals based on the control, wherein mapping the plurality of first signals to the plurality of second signals comprises providing the plurality of first signals, circularly rotated by an amount equal to the fractional data weight of the input data, as the plurality of second signals; and 
 selecting zero or more of a plurality of circuit elements based on the plurality of second signals. 
 
     
     
       21. The method of  claim 20 , further comprising:
 providing the fractional data weight as a value between zero and the value of the input data, inclusive, rounded up or down to the nearest whole number. 
 
     
     
       22. The method of  claim 20 , wherein the asserting zero or more of the plurality of first signals includes asserting zero or more of the plurality of first signals based on thermometer decoding of the input data. 
     
     
       23. The method of  claim 20 , further comprising:
 accumulating a current value of the control with the fractional data weight of the input data to obtain a new value of the control. 
 
     
     
       24. An apparatus, comprising:
 means for asserting zero or more of a plurality of first signals based on input data; 
 means for generating a control using a fractional data weight of the input data; 
 means for mapping the plurality of first signals to a plurality of second signals based on the control, wherein the means for mapping the plurality of first signals to the plurality of second signals is configured to provide the plurality of first signals, circularly rotated by an amount equal to the fractional data weight of the input data, as the plurality of second signals; and 
 means for selecting zero or more of a plurality of circuit elements based on the plurality of second signals. 
 
     
     
       25. The apparatus of  claim 24 , further comprising:
 means for providing the fractional data weight as a value between zero and the value of the input data, inclusive, rounded up or down to the nearest whole number. 
 
     
     
       26. The apparatus of  claim 24 , wherein the means for asserting zero or more of the plurality of first signals is configured to assert zero or more of the plurality of first signals based on thermometer decoding of the input data. 
     
     
       27. The apparatus of  claim 24 , further comprising:
 means for accumulating a current value of the control with the fractional data weight of the input data to obtain a new value of the control. 
 
     
     
       28. A digital-to-analog converter (DAC) for converting digital input data to an analog output signal, the DAC comprising:
 a first plurality of circuit elements of equal size configured to generate the analog output signal; 
 a first thermometer decoder to receive at least a first portion of the digital input data and to provide a plurality of first signals; and 
 a first dynamic element matching (DEM) unit to receive the plurality of first signals and to provide a plurality of second signals used to select the first plurality of circuit elements, the first DEM unit mapping the plurality of first signals to the plurality of second signals based on a fractional data weight of the at least first portion of the digital input data, wherein the first DEM unit comprises:
 a plurality of multiplexers, each multiplexer configured to receive the plurality of first signals in a different order and configured to provide one of the plurality of second signals; and 
 a control circuit to generate a control for the plurality of multiplexers based on the fractional data weight of the at least a first portion of the digital input data. 
 
 
     
     
       29. The DAC of  claim 28 , wherein the control circuit accumulates the fractional data weight of the at least a first portion of the digital input data with a current value of the control to obtain a new value of the control. 
     
     
       30. The DAC of  claim 28 , wherein the first plurality of circuit elements includes a plurality of current sources to provide equal amount of current. 
     
     
       31. The DAC of  claim 28 , wherein the first plurality of circuit elements includes a plurality of capacitors of equal size. 
     
     
       32. The DAC of  claim 28 , further comprising:
 a second plurality of circuit elements of equal size configured to generate the analog output signal; and 
 a second thermometer decoder to receive a second portion of the digital input data and to provide a plurality of third signals used to select the second plurality of circuit elements, the first and second portions of the digital input data being non-overlapping and each including at least one bit of the digital input data. 
 
     
     
       33. The DAC of  claim 32 , wherein the second plurality of circuit elements includes a plurality of current sources to provide equal amount of current. 
     
     
       34. The DAC of  claim 32 , wherein the second plurality of circuit elements includes a plurality of capacitors of equal size. 
     
     
       35. The DAC of  claim 28 , further comprising:
 a second plurality of circuit elements of equal size configured to generate the analog output signal; and 
 a second thermometer decoder to receive a second portion of the digital input data and to provide a plurality of third signals, the first and second portions of the digital input data being non-overlapping and each including at least one bit of the digital input data; and 
 a second DEM unit to receive the plurality of third signals and to provide a plurality of fourth signals used to select the second plurality of circuit elements, the second DEM unit configured to map the plurality of third signals to the plurality of fourth signals based on a fractional data weight of the second portion of the digital input data. 
 
     
     
       36. The DAC of  claim 35 , wherein the second DEM unit includes:
 a plurality of multiplexers, each multiplexer configured to receive the plurality of third signals in a different order and to provide one of the plurality of fourth signals; and 
 a control circuit to generate a control for the plurality of multiplexers based on the fractional data weight of the second portion of the digital input data. 
 
     
     
       37. The DAC of  claim 36 , wherein the control circuit accumulates the fractional data weight of the second portion of the digital input data with a current value of the control to obtain a new value of the control. 
     
     
       38. The DAC of  claim 35 , wherein the second plurality of circuit elements includes a plurality of current sources providing equal amount of current. 
     
     
       39. The DAC of  claim 35 , wherein the second plurality of circuit elements includes a plurality of capacitors of equal size. 
     
     
       40. The DAC of  claim 35 , further comprising:
 an circuit element array including the first and second plurality of circuit elements, the circuit element array configured to generate the analog output signal; 
 a column decoder to generate a plurality of fifth signals used to select a column of the circuit element array based on one of the plurality of second or fourth signals; and 
 a row decoder to generate a plurality of sixth signals used to select a row of the circuit element array based on the other of the plurality of second or fourth signals.