Reconfigurable bit-manipulation node

Abstract

A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

1. A Programmable bit-shifter comprising:
 a circuit configured to receive a plurality of input bits; and 
 a circuit configured to perform an exclusive-or (XOR) function on multiple shifted versions of the plurality of input bits; 
 where the shifter is programmable on a cycle-by-cycle basis. 
 
     
     
       2. The shifter of  claim 1  wherein the shifter is programmable to implement a parallel linear feedback shift register. 
     
     
       3. The shifter of  claim 2  wherein the parallel linear feedback shifter register includes a parallel maskable linear feedback shifter register. 
     
     
       4. A reconfigurable bit manipulation node utilizing the shifter as recited in  claim 1 . 
     
     
       5. The shifter of  claim 1 , wherein the shifter is programmable to implement a convolutional encoder. 
     
     
       6. The shifter of  claim 1 , wherein the shifter is programmable to implement a scrambler. 
     
     
       7. The shifter of  claim 1 , wherein the shifter is programmable to implement Galois multiplication. 
     
     
       8. The shifter of  claim 3 , wherein the parallel maskable linear feedback shifter register is an 18-bit linear feedback shifter register. 
     
     
       9. The shifter of  claim 1 , wherein the shifter is configured to implement a channel coding scheme for wireless communication. 
     
     
       10. The shifter of  claim 1 , wherein the shifter is configured to implement an error correcting scheme comprising at least one of:
 error detecting cyclic codes; 
 error detecting and correcting hamming codes; and 
 single burst error correcting fire code.