Techniques to perform forward error correction for an electrical backplane

Abstract

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

1. An apparatus, comprising:
 a physical layer unit having a forward error correction (FEC) sublayer to perform FEC using a transcode bit to represent a two bit synchronization header, said FEC sublayer having an FEC encoder to encode a physical coding sublayer (PCS) block by compressing said two bit synchronization header into said transcode bit, and to use one bit of the two bit synchronization header in the PCS block to send parity information, the parity information and transcode bit to be placed in an FEC block prior to transmission of the FEC block over a physical medium. 
 
     
     
       2. The apparatus of  claim 1 , wherein the FEC block has 2112 bits including 32 parity bits and 32 65-bit blocks with each 65-bit block including one transcode bit. 
     
     
       3. The apparatus of  claim 2 , wherein the 32 parity bits are placed at the end of the FEC block. 
     
     
       4. The apparatus of  claim 1 , wherein the FEC sublayer further comprising:
 a reverse gearbox; 
 a compressor to couple to said reverse gearbox; 
 a selector to couple to said compressor; 
 a parity generator to couple to said compressor;
 a multiplexer to couple to said compressor, selector and said parity generator; 
 
 a scrambler to couple to said multiplexer; and 
 a pseudo-noise generator to couple to said scrambler. 
 
     
     
       5. The apparatus of  claim 1 , wherein the PCS block has 66 bits including the two bit synchronization header. 
     
     
       6. The apparatus of  claim 1 , wherein the value of the transcode bit corresponds to the value of a second bit in the two bit synchronization header. 
     
     
       7. The apparatus of  claim 1 , comprising a forward error correction decoder and
 block synchronizer to decode a physical coding sublayer block of information by reconstructing said two bit synchronization header using said single bit. 
 
     
     
       8. The apparatus of  claim 1 , comprising a forward error correction decoder and block synchronizer to comprise:
 a descrambler;
 a pseudo-noise generator to couple to said descrambler; 
 a synchronizer to couple to said descrambler; a decoder to couple to said synchronizer; an error monitor to couple to said decoder; and 
 
 a reconstructor to couple to said decoder. 
 
     
     
       9. A method comprising
 performing forward error correction (FEC) using a transcode bit to represent a two bit synchronization header, said performing comprising: 
 encoding a physical coding sublayer (PCS) block of information by compressing said two bit synchronization header into said transcode bit; 
 using one bit of the two bit synchronization header in the PCS block to send parity information; and 
 placing said transcode bit and said parity information in an FEC block prior to transmission of the FEC block over a physical medium. 
 
     
     
       10. The method of  claim 9 , wherein the PCS block has 66 bits including the two bit synchronization header. 
     
     
       11. The method of  claim 9 , wherein the value of the transcode bit corresponds to the value of a second bit in the two bit synchronization header. 
     
     
       12. The method of  claim 9 , comprising:
 receiving PCS blocks of information; 
 compressing two synchronization bits from each PCS block to a transcode bit; and 
 generating the forward error correction block using said PCS blocks and said parity information. 
 
     
     
       13. The method of  claim 12 , wherein the FEC block has 2112 bits including 32 parity bits and 32 65-bit blocks with each 65-bit block including one transcode bit. 
     
     
       14. The method of  claim 13 , wherein the 32 parity bits are placed at the end of the FEC block. 
     
     
       15. The method of  claim 12 , wherein the FEC block has 2112 bits including 32 parity bits and 32 65-bit blocks with each 65-bit block including one transcode bit. 
     
     
       16. The method of  claim 9 , comprising:
 decoding a physical medium attachment (PMA) sublayer block of information by reconstructing said two bit synchronization header using said transcode bit. 
 
     
     
       17. The method of  claim 9 , comprising:
 receiving physical medium attachment (PMA) sublayer blocks of information; 
 decoding each PMA block; 
 retrieving parity check bits for said PMA sublayer blocks; and 
 performing forward error correction using said parity check bits. 
 
     
     
       18. An article comprising a machine-readable storage medium containing instructions that if executed enable a system to
 perform forward error correction (FEC) using a transcode bit to represent a two bit synchronization header by:
 encoding a physical coding sublayer (PCS) block of information by compressing said two bit synchronization header into said transcode bit; 
 using one bit of the two bit synchronization header in the PCS block to send parity information; and 
 placing said transcode bit and said parity information in an FEC block prior to transmission of the FEC block over a physical medium. 
 
 
     
     
       19. The article of  claim 18 , wherein the value of the transcode bit corresponds to the value of a second bit in the two bit synchronization header.