Phase change memory device capable of satisfying reset current characteristic and contact resistance characteristic

Abstract

A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

1. A phase change memory device comprising:
 a semiconductor substrate provided with a switching device; 
 a lower electrode contact formed over the switching device, the lower electrode contact having a specific resistance which increases from a lower part to an upper part of the lower electrode contact; and 
 a phase change pattern layer formed on the lower electrode contact, 
 wherein the lower electrode contact includes: 
 a crystalline conductive layer formed over the switching device; and 
 an amorphous conductive layer formed over the crystalline conductive layer. 
 
     
     
       2. The phase change memory device of  claim 1 , wherein the crystalline and amorphous conductive layers each comprise an SEG (Selective Epitaxial Growth) layer. 
     
     
       3. The phase change memory device of  claim 1 , wherein the crystalline conductive layer is thicker than the amorphous conductive layer. 
     
     
       4. A phase change memory device comprising:
 a semiconductor substrate provided with a switching device; 
 a lower electrode contact formed over the switching device, the lower electrode contact having a specific resistance which increases from a lower part to an upper part of the lower electrode contact; and 
 a phase change pattern layer formed on the lower electrode contact, 
 
       wherein the lower electrode contact includes:
 a first SEG (Selective Epitaxial Growth) layer formed over the switching device, the first SEG layer having conductive impurities at a first density; and 
 a second SEG layer formed on the first SEG layer, wherein the second SEG layer has conductive impurities at a second density such that the second density is less than the first density. 
 
     
     
       5. The phase change memory device of  claim 4 , wherein the conductive impurities are p-type impurities. 
     
     
       6. The phase change memory device of  claim 4 , wherein the second SEG layer is undoped and only has intrinsic levels of conductive impurities. 
     
     
       7. The phase change memory device of  claim 4 , wherein the first SEG layer is thicker than the second SEG layer. 
     
     
       8. A phase change memory device comprising:
 a semiconductor substrate provided with a switching device; 
 a lower electrode contact formed over the switching device, the lower electrode contact having a specific resistance which increases from a lower part to an upper part of the lower electrode contact; and 
 a phase change pattern layer formed on the lower electrode contact, 
 
       wherein the lower electrode contact comprises:
 a germanium-rich SiGe SEG (Selective Epitaxial Growth) layer formed over the switching device wherein the germanium-rich SiGe SEG layer comprises a Si x Ge (1-x)  stoichiometric ratio where x<0.45; and 
 a silicon-rich SiGe SEG layer formed over the germanium-rich SiGe SEG wherein the silicon-rich SiGe SEG layer comprises a Si x Ge (1-x)  stoichiometric ratio where x>0.55. 
 
     
     
       9. The phase change memory device of  claim 8 , further comprising a normal SiGe SEG layer formed over the silicon-rich SiGe SEG layer, wherein the normal SiGe SEG layer having a stoichiometric ratio of Si x Ge 1-x  where x is between 0.45 and 0.55. 
     
     
       10. A phase change memory device comprising:
 a semiconductor substrate provided with a switching device; 
 a lower electrode contact formed over the switching device, the lower electrode contact having a specific resistance which increases from a lower part to an upper part of the lower electrode contact; and 
 a phase change pattern layer formed on the lower electrode contact, 
 
       wherein the lower electrode contact comprises:
 a SiGe SEG (Selective Epitaxial Growth) layer formed over the switching device; and 
 a Si SEG layer formed over the SiGe SEG layer.