Bias circuit and voltage-controlled oscillator

Abstract

A bias circuit and a voltage-controlled oscillator (VCO) thereof suitable for improving the stability of the bias circuit are provided. The bias circuit includes: an error amplifier circuit, having an inverting input terminal connected to a reference voltage; a voltage-controlled current source, having a voltage control terminal connected to a voltage output terminal of the error amplifier circuit, in which a current generated by the current source is controlled by a voltage at the voltage output terminal of the error amplifier circuit; a delay control circuit, having a current input terminal connected to the voltage-controlled current source, an output terminal connected to a non-inverting input terminal of the error amplifier circuit, and a voltage input terminal connected to a supply terminal of the control voltage, and the delay control circuit is adapted to adjust an output voltage of the delay control circuit according to a control voltage.

1. A bias circuit, comprising:
 an error amplifier circuit, having an inverting input terminal connected to a reference voltage; 
 a voltage-controlled current source, having a voltage control terminal connected to a voltage output terminal of the error amplifier circuit, wherein the current amount of the voltage-controlled current source is controlled by a voltage at the voltage output terminal of the error amplifier circuit; and 
 a delay control circuit, having a current input terminal connected to the voltage-controlled current source, an output terminal connected to a non-inverting input terminal of the error amplifier circuit, and a voltage input terminal connected to a supply terminal of the control voltage; wherein 
 the delay control circuit is adapted to adjust an output voltage of the delay control circuit according to the control voltage. 
 
     
     
       2. The bias circuit according to  claim 1 , wherein
 the voltage-controlled current source is a Negative Metal-Oxide-Semiconductor (NMOS) tube, with a gate connected to the voltage output terminal of the error amplifier circuit, a drain connected to the current input terminal of the delay control circuit, and a source connected to the ground. 
 
     
     
       3. The bias circuit according to  claim 2 , wherein the error amplifier circuit comprises:
 a non-inverting input terminal; 
 an inverting input terminal; 
 a voltage output terminal; 
 a first Metal-Oxide-Semiconductor (MOS) tube; 
 a second MOS tube, having a gate connected to a gate of the first MOS tube, and a source connected to a source of the first MOS tube, wherein the gate of the first MOS tube is connected to a drain of itself; 
 a third MOS tube, having a gate connected to the non-inverting input terminal, and a drain connected to the drain of the first MOS tube; 
 a fourth MOS tube, having a gate connected to the inverting input terminal, and a drain connected to a drain of the second MOS tube, wherein the drain of the second MOS tube and the drain of the fourth MOS tube are connected to the voltage output terminal; and 
 a fifth MOS tube, having a gate connected to a bias voltage, and a drain connected to a source of the third MOS tube and a source of the fourth MOS tube; 
 wherein, when the voltage-controlled current source tube is a NMOS tube, a source of the fifth MOS tube is connected to the working voltage supply terminal; when the voltage-controlled current source tube is a PMOS tube, the source of the fifth MOS tube is connected to the ground. 
 
     
     
       4. The bias circuit according to  claim 1 , wherein
 the voltage-controlled current source is a Positive Metal-Oxide-Semiconductor (PMOS) tube, with a gate connected to the voltage output terminal of the error amplifier circuit, a drain connected to the current input terminal of the delay control circuit, and a source connected to a working voltage supply terminal. 
 
     
     
       5. The bias circuit according to  claim 4 , wherein the error amplifier circuit comprises:
 a non-inverting input terminal; 
 an inverting input terminal; 
 a voltage output terminal; 
 a first Metal-Oxide-Semiconductor (MOS) tube; 
 a second MOS tube, having a gate connected to a gate of the first MOS tube, and a source connected to a source of the first MOS tube, wherein the gate of the first MOS tube is connected to a drain of itself; 
 a third MOS tube, having a gate connected to the non-inverting input terminal, and a drain connected to the drain of the first MOS tube; 
 a fourth MOS tube, having a gate connected to the inverting input terminal, and a drain connected to a drain of the second MOS tube, wherein the drain of the second MOS tube and the drain of the fourth MOS tube are connected to the voltage output terminal; and 
 a fifth MOS tube, having a gate connected to a bias voltage, and a drain connected to a source of the third MOS tube and a source of the fourth MOS tube; 
 wherein, when the voltage-controlled current source tube is a NMOS tube, a source of the fifth MOS tube is connected to the working voltage supply terminal; when the voltage-controlled current source tube is a PMOS tube, the source of the fifth MOS tube is connected to the ground. 
 
     
     
       6. The bias circuit according to  claim 1 , wherein the delay control circuit comprises:
 an output terminal; 
 a sixth MOS tube, having a drain connected to the output terminal, a source connected to the voltage-controlled current source, and a gate connected to the ground; and 
 a voltage-controlled resistor, connected to the sixth MOS tube, wherein a control voltage is applied to a voltage control terminal of the voltage-controlled resistor. 
 
     
     
       7. The bias circuit according to  claim 6 , wherein the voltage-controlled resistor comprises:
 a seventh MOS tube, having a gate applied with the control voltage; and 
 an eighth MOS tube, having a drain connected to a drain of the seventh MOS tube, a source connected to a source of the seventh MOS tube and connected to the ground, and a gate connected to the drain of itself. 
 
     
     
       8. The bias circuit according to  claim 1 , wherein the delay control circuit comprises:
 an output terminal; 
 a sixth MOS tube, having a drain connected to the output terminal, a source connected to the voltage-controlled current source, and a gate connected to a working voltage supply terminal; and 
 a voltage-controlled resistor, connected to the sixth MOS tube, wherein a control voltage is applied to a voltage control terminal of the voltage-controlled resistor. 
 
     
     
       9. The bias circuit according to  claim 8 , wherein the voltage-controlled resistor comprises:
 a seventh MOS tube, having a gate applied with the control voltage; and 
 an eighth MOS tube, having a drain connected to a drain of the seventh MOS tube, a source connected to a source of the seventh MOS tube and connected to the working voltage supply terminal, and a gate connected to the source of itself. 
 
     
     
       10. A voltage-controlled oscillator (VCO), comprising:
 a reference voltage supply terminal, adapted to provide a reference voltage; 
 a supply terminal of a control voltage, adapted to provide the control voltage; 
 a bias circuit, adapted to generate an output voltage under the control of the reference voltage supplied by the reference voltage supply terminal and the control voltage supplied by the supply terminal of the control voltage; 
 a delay unit, adapted to generate a differential signal according to the output voltage of an error amplifier circuit and the control voltage output by the supply terminal of the control voltage; 
 an error amplifier circuit, having an inverting input terminal connected to the reference voltage; 
 a voltage-controlled current source, having a voltage control terminal connected to a voltage output terminal of the error amplifier circuit, wherein the current amount of the voltage-controlled current source is controlled by a voltage at the voltage output terminal of the error amplifier circuit; 
 a delay control circuit, having a current input terminal connected to the voltage-controlled current source, an output terminal connected to a non-inverting input terminal of the error amplifier circuit, and a voltage input terminal connected to the supply terminal of the control voltage; wherein 
 the delay control circuit is adapted to adjust an output voltage of the delay control circuit according to the control voltage. 
 
     
     
       11. The voltage-controlled oscillator according to  claim 10 , wherein
 the voltage-controlled current source is a Negative Metal-Oxide-Semiconductor (NMOS) tube, with a gate connected to the voltage output terminal of the error amplifier circuit, a drain connected to the current input terminal of the delay control circuit, and a source connected to the ground. 
 
     
     
       12. The voltage-controlled oscillator according to  claim 11 , wherein the error amplifier circuit comprises:
 a non-inverting input terminal; 
 an inverting input terminal; 
 a voltage output terminal; 
 a first Metal-Oxide-Semiconductor (MOS) tube; 
 a second MOS tube, having a gate connected to a gate of the first MOS tube, and a source connected to a source of the first MOS tube, wherein the gate of the first MOS tube is connected to a drain of itself; 
 a third MOS tube, having a gate connected to the non-inverting input terminal, and a drain connected to the drain of the first MOS tube; 
 a fourth MOS tube, having a gate connected to the inverting input terminal, and a drain connected to a drain of the second MOS tube, wherein the drain of the second MOS tube and the drain of the fourth MOS tube are connected to the voltage output terminal; and 
 a fifth MOS tube, having a gate connected to a bias voltage, and a drain connected to a source of the third MOS tube and a source of the fourth MOS tube; 
 wherein, when the voltage-controlled current source tube is a NMOS tube, a source of the fifth MOS tube is connected to the working voltage supply terminal; when the voltage-controlled current source tube is a PMOS tube, the source of the fifth MOS tube is connected to the ground. 
 
     
     
       13. The voltage-controlled oscillator according to  claim 10 , wherein
 the voltage-controlled current source is a Positive Metal-Oxide-Semiconductor (PMOS) tube, with a gate connected to the voltage output terminal of the error amplifier circuit, a drain connected to the current input terminal of the delay control circuit, and a source connected to a working voltage supply terminal. 
 
     
     
       14. The voltage-controlled oscillator according to  claim 13 , wherein the error amplifier circuit comprises:
 a non-inverting input terminal; 
 an inverting input terminal; 
 a voltage output terminal; 
 a first Metal-Oxide-Semiconductor (MOS) tube; 
 a second MOS tube, having a gate connected to a gate of the first MOS tube, and a source connected to a source of the first MOS tube, wherein the gate of the first MOS tube is connected to a drain of itself; 
 a third MOS tube, having a gate connected to the non-inverting input terminal, and a drain connected to the drain of the first MOS tube; 
 a fourth MOS tube, having a gate connected to the inverting input terminal, and a drain connected to a drain of the second MOS tube, wherein the drain of the second MOS tube and the drain of the fourth MOS tube are connected to the voltage output terminal; and 
 a fifth MOS tube, having a gate connected to a bias voltage, and a drain connected to a source of the third MOS tube and a source of the fourth MOS tube; 
 wherein, when the voltage-controlled current source tube is a NMOS tube, a source of the fifth MOS tube is connected to the working voltage supply terminal; when the voltage-controlled current source tube is a PMOS tube, the source of the fifth MOS tube is connected to the ground. 
 
     
     
       15. The voltage-controlled oscillator according to  claim 10 , wherein the delay control circuit comprises:
 an output terminal; 
 a sixth MOS tube, having a drain connected to the output terminal, a source connected to the voltage-controlled current source, and a gate connected to the ground; and 
 a voltage-controlled resistor, connected to the sixth MOS tube, wherein a control voltage is applied to a voltage control terminal of the voltage-controlled resistor. 
 
     
     
       16. The voltage-controlled oscillator according to  claim 15 , wherein the voltage-controlled resistor comprises:
 a seventh MOS tube, having a gate applied with the control voltage; and 
 an eighth MOS tube, having a drain connected to a drain of the seventh MOS tube, a source connected to a source of the seventh MOS tube and connected to the ground, and a gate connected to the drain of itself. 
 
     
     
       17. The voltage-controlled oscillator according to  claim 10 , wherein the delay control circuit comprises:
 an output terminal; 
 a sixth MOS tube, having a drain connected to the output terminal, a source connected to the voltage-controlled current source, and a gate connected to a working voltage supply terminal; and 
 a voltage-controlled resistor, connected to the sixth MOS tube, wherein a control voltage is applied to a voltage control terminal of the voltage-controlled resistor. 
 
     
     
       18. The voltage-controlled oscillator according to  claim 17 , wherein the voltage-controlled resistor comprises:
 a seventh MOS tube, having a gate applied with the control voltage; and 
 an eighth MOS tube, having a drain connected to a drain of the seventh MOS tube, a source connected to a source of the seventh MOS tube and connected to the working voltage supply terminal, and a gate connected to the source of itself.