External compensation for input current source

Abstract

An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.

1. A compensation circuit, for compensating an external supply voltage, the compensation circuit comprising:
 an operational amplifier, having a bias voltage as a first input of the operational amplifier, and a second input; 
 a first PMOS pair, coupled to the output of the operational amplifier and the external supply voltage, where the output of the first PMOS pair is the second input of the operational amplifier; 
 a second PMOS pair, coupled to the output of the operational amplifier and the external supply voltage, where the output of the second PMOS pair is an output voltage of the compensation circuit, and is equal to the input voltage −χΔV; 
 a first NMOS circuit, coupled to the first and second PMOS pair by means of a blend connection, and coupled to the external supply voltage, a reference voltage, and a nominal voltage, for providing an output voltage equal to the reference voltage—the nominal voltage/3−χΔV; and 
 a second NMOS circuit, coupled to the first NMOS circuit and the external supply voltage, for providing an output voltage equal to the external supply voltage/3. 
 
     
     
       2. The compensation circuit of  claim 1 , wherein the first NMOS circuit comprises:
 a first NMOS pair, a second NMOS pair, and a third NMOS pair, the output of the first NMOS pair is coupled to the first PMOS pair, and the outputs of the second NMOS pair and the third NMOS pair are coupled to the second PMOS pair by means of the blend connection; 
 and the second NMOS circuit comprises: 
 a first NMOS; 
 a second NMOS; and 
 a third NMOS; 
 wherein a VGS of the first NMOS, the second NMOS and the third NMOS is the same. 
 
     
     
       3. The compensation circuit of  claim 2 , wherein a gain of the first NMOS pair and the third NMOS pair is controlled so that χ is a number between 0 and ⅓. 
     
     
       4. The compensation circuit of  claim 1 , being implemented in an integrated circuit comprising at least a pre-driver, for providing the output voltage to the pre-driver that is compensated for with supply voltage variations. 
     
     
       5. An integrated circuit, comprising:
 a pre-driver stage, coupled to an external supply voltage, for controlling final driver stage voltage; 
 a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; 
 a compensation circuit, coupled to the pre-driver stage, for providing a first bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage, comprising:
 an operational amplifier, having a second bias voltage as a first input of the operational amplifier, and a second input; 
 a first PMOS pair, coupled to the output of the operational amplifier and the external supply voltage, where the output of the first PMOS pair is the second input of the operational amplifier; 
 a second PMOS pair, coupled to the output of the operational amplifier and the external supply voltage, where the output of the second PMOS pair is an output voltage of the compensation circuit, and is equal to the input voltage −χΔV; 
 
 a first NMOS circuit, coupled to the first and second PMOS pair by means of a blend connection, and coupled to the external supply voltage, a reference voltage, and a nominal voltage, for providing an output voltage equal to the reference voltage−the nominal voltage/3 −χΔV; and 
 a second NMOS circuit, coupled to the first NMOS circuit and the external supply voltage, for providing an output voltage equal to the external supply voltage/3, which is output to the pre-driver stage as the first bias voltage; and 
 a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing the second bias voltage to the compensation circuit. 
 
     
     
       6. The integrated circuit of  claim 5 , wherein the pre-driver stage comprises an n-channel and a p-channel, the first bias voltage output by the compensation circuit is input to the n-channel of the pre-driver stage, and the integrated circuit further comprises:
 a current mirror, comprising an NMOS PMOS pair, coupled to the first bias voltage output by the compensation circuit, and the p-channel of the pre-driver stage, for mirroring the bias current through the p-channel stage to control current through the p-channel stage. 
 
     
     
       7. The compensation circuit of  claim 5 , wherein the first NMOS circuit comprises:
 a first NMOS pair, a second NMOS pair, and a third NMOS pair, the output of the first NMOS pair is coupled to the first PMOS pair, and the outputs of the second NMOS pair and the third NMOS pair are coupled to the second PMOS pair by means of the blend connection; 
 and the second NMOS circuit comprises: 
 a first NMOS; 
 a second NMOS; and 
 a third NMOS; 
 wherein a VGS of the first NMOS, the second NMOS and the third NMOS is the same. 
 
     
     
       8. The compensation circuit of  claim 7 , wherein a gain of the first NMOS pair and the third NMOS pair is controlled so that χ is a number between 0 and ⅓.