Semiconductor device having super junction structure

Abstract

A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.

1. A semiconductor device comprising:
 a silicon substrate that has a first conductivity type, that has a (110)-oriented surface, and that provides a drain region; 
 a PN column layer that is made of a silicon epitaxial layer and that includes a plurality of first columns having the first conductivity type and a plurality of second columns having a second conductivity type, wherein each of the first columns and the second columns has an approximately rectangular parallelepiped shape, and the plurality of the first columns and the plurality of the second columns are alternately arranged on the (110)-oriented surface of the silicon substrate in a planer direction of the silicon substrate in such a manner that the plurality of first columns contacts the plurality of second columns on a (111)-oriented surface, respectively; 
 a channel-forming layer that is made of a silicon layer, that has the second conductivity type, and that is disposed on the PN column layer; 
 a plurality of source regions that has the first conductivity type and that is disposed at a surface portion of the channel-forming layer; and 
 a plurality of gate electrodes that has an approximately rectangular parallelepiped shape, that is disposed to penetrate through the channel-forming layer, and that is arranged adjacent to the plurality of source regions, respectively, wherein each of the gate electrodes has side surfaces that cross the contact surfaces of the plurality of first columns and the plurality of second columns in a plane of the silicon substrate, and each of the side surfaces of the plurality of gate electrodes contacts a (112)-oriented surface of the channel-forming layer. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein:
 the plurality of gate electrodes is arranged in a plane of the silicon substrate at a predetermined interval; and 
 the predetermined interval is less than or equal to 40 μm. 
 
     
     
       3. The semiconductor device according to  claim 2 , wherein the predetermined interval is less than or equal to 20 μm. 
     
     
       4. The semiconductor device according to  claim 2 , wherein the predetermined interval is greater than or equal to 5 μm. 
     
     
       5. The semiconductor device according to  claim 4 , wherein the predetermined interval is greater than or equal to 10 μm. 
     
     
       6. A semiconductor device comprising:
 a silicon substrate that has a first conductivity type, that has a (110)-oriented surface, and that provides a drain region; 
 a PN column layer that is made of a silicon epitaxial layer and that includes a plurality of first columns having the first conductivity type and a plurality of second columns having a second conductivity type, wherein each of the first columns and the second columns has an approximately rectangular parallelepiped shape, and the plurality of the first columns and the plurality of the second columns are alternately arranged on the (110)-oriented surface of the silicon substrate in a planer direction of the silicon substrate in such a manner that the plurality of first columns contacts the plurality of second columns on a (111)-oriented surface, respectively; 
 a channel-forming layer that is made of a silicon layer, that has the second conductivity type, and that is disposed on the PN column layer; 
 a plurality of source regions that has the first conductivity type and that is disposed at a surface portion of the channel-forming layer; and 
 a plurality of gate electrodes that has an approximately rectangular parallelepiped shape, that is disposed to penetrate through the channel-forming layer, and that is arranged adjacent to the plurality of source regions, respectively, wherein each of the gate electrodes has side surfaces that cross the contact surfaces of the plurality of first columns and the plurality of second columns in a plane of the silicon substrate, and each of the side surfaces of the plurality of gate electrodes contacts a (100)-oriented surface of the channel-forming layer. 
 
     
     
       7. The semiconductor device according to  claim 6 , wherein
 the plurality of gate electrodes is arranged in a plane of the silicon substrate at a predetermined interval, and 
 the predetermined interval is less than or equal to 40 μm. 
 
     
     
       8. The semiconductor device according to  claim 7 , wherein the predetermined interval is less than or equal to 20 μm. 
     
     
       9. The semiconductor device according to  claim 7 , wherein the predetermined interval is greater than or equal to 5 μm. 
     
     
       10. The semiconductor device according to  claim 9 , wherein the predetermined interval is greater than or equal to 10 μm.