Encoding a gray code sequence for an odd length sequence

Abstract

A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

1. A method for generating a gray code from a binary value, the method comprising:
 receiving a binary value from a binary generator and a cycle flag from a cycle toggle; 
 generating an intermediate value from the cycle flag and the binary value; and 
 converting the intermediate value into the gray code corresponding to the intermediate value with a gray converter. 
 
     
     
       2. The method as claimed in  claim 1 , further comprising:
 receiving L binary values, where L is an odd positive integer; and 
 generating a gray code sequence from the L binary values. 
 
     
     
       3. A method for generating a gray code from a binary value, the method comprising:
 generating an intermediate value from a cycle flag and the binary value: 
 setting the most significant bit of the intermediate value equal to the cycle flag, and setting the remaining bits of the intermediate value equal to the binary value; and 
 converting the intermediate value into the gray code corresponding to the intermediate value. 
 
     
     
       4. The method as claimed in  claim 3 , wherein the most significant bit of the intermediate value is set equal to the cycle flag and the remaining bits of the intermediate value are set equal to the binary value if the cycle flag is equal to a first value. 
     
     
       5. The method as claimed in  claim 4 , wherein the significant bit is set equal to “1”. 
     
     
       6. A method for generating a gray code from a binary value, the method comprising:
 receiving L binary values, where L is an odd positive integer; 
 generating an intermediate value from a cycle flag and the L binary values; 
 setting the most significant bit of the intermediate value equal to the cycle flag, and setting the remaining bits of the intermediate value equal to (B+C−L), where B is the binary value, where C is 2 raised to the n power, where n is the number of bits in B; and 
 converting the intermediate value into the gray code corresponding to the intermediate value. 
 
     
     
       7. The method as claimed in  claim 6 , wherein the most significant bit of the intermediate value is set equal to logic “0”. 
     
     
       8. An apparatus for generating a gray code from a binary value comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value; an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value; and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code. 
     
     
       9. An apparatus for generating a gray code from a binary value comprising; a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value; an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value; and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code;
 wherein the cycle flag toggle circuit comprises a comparator configured to receive the binary value and compare the number of binary values received to a predetermined length of binary values L; a 2:1 multiplexer having a first input, a second input, and a control line coupled to the output of the comparator; and a flip flop coupled to the output of the 2:1 multiplexer and also coupled to the input of the intermediate value generator. 
 
     
     
       10. The apparatus as claimed in  claim 9 , wherein the first input is selected when the control line equals to logic “0”. 
     
     
       11. The apparatus as claimed in  claim 9 , wherein the second input is selected when the control line equals to logic “1”. 
     
     
       12. An apparatus for generating a gray code from a binary value comprising a cycle flap toggle circuit configured to toggle a cycle flag between a first value and a second value; an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value; and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code;
 wherein the intermediate value generator comprises an adder configured to add the binary value to the value of C minus L, where C is 2 raised to the power of n, where n is the number of bits of the binary value, and where L is the length of the binary sequence; a 2:1 multiplexer having a first input coupled to the output of the adder; a second input configured to receive the binary value, and a control line coupled to the output of the cycle toggle flag circuit; and a mixer having a first input coupled to the output of the multiplexer, a second input coupled to the output of the cycle flag toggle and an output coupled to the binary to gray converter, configured to join the output value from the multiplexer and the output of the cycle toggle flag circuit.