ESD configuration for low parasitic capacitance I/O

Abstract

An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.

1. An integrated circuit comprising:
 an input/output (I/O) pad; 
 an internal circuit biased with a first voltage supply and a second voltage supply, wherein the internal circuit is connected to the I/O pad at a first node; 
 an electrostatic discharge (ESD) protection circuit connected between the first node and a second node; and 
 an inductor connected between the second node and a third voltage supply. 
 
     
     
       2. The integrated circuit of  claim 1 , further comprising an ESD clamp connected between the second node and the second voltage supply. 
     
     
       3. The integrated circuit of  claim 2 , wherein the ESD clamp is configured to shunt ESD current from the ESD protection circuit during a positive I/O ESD event. 
     
     
       4. The integrated circuit of  claim 3 , further comprising:
 a second ESD protection circuit coupled between the first node and a fourth voltage supply; and 
 a second ESD clamp configured to shunt ESD current from the second ESD protection circuit during a negative I/O ESD event. 
 
     
     
       5. The integrated circuit of  claim 1 , wherein:
 the first voltage supply comprises a first positive voltage; 
 the second voltage supply comprises ground; and 
 the third voltage supply comprises a second positive voltage, wherein the second positive voltage is greater than the first positive voltage. 
 
     
     
       6. The integrated circuit of  claim 1 , wherein the third voltage supply is configured to provide a reverse bias voltage across the ESD protection circuit to reduce a parasitic capacitance. 
     
     
       7. The integrated circuit of  claim 1 , wherein the inductor is configured to transfer voltage from the third voltage supply to the second node in a first frequency range and to block voltage from third voltage supply to the second node in a second frequency range. 
     
     
       8. The integrated circuit of  claim 7 , wherein the inductor is configured to have a relatively low impedance when a signal with a relatively low frequency is present on the I/O pad and to have a relatively high impedance when a signal with a relatively high frequency is present on the I/O pad. 
     
     
       9. The integrated circuit of  claim 1 , wherein the inductor comprises at least one of a discrete component external to the integrated circuit, a discrete component internal to the integrated package, and a package component internal to the integrated circuit. 
     
     
       10. The integrated circuit of  claim 1 , further comprising an ESD clamp connected between the first voltage supply and the second voltage supply. 
     
     
       11. The integrated circuit of  claim 1 , further comprising:
 a second I/O pad, wherein the internal circuit is connected to the second I/O pad at a third node; 
 a second ESD protection circuit connected between the third node and a fourth node; and 
 a second inductor connected between the fourth node and the third voltage supply. 
 
     
     
       12. The integrated circuit of  claim 11 , further comprising:
 a first ESD clamp connected between the first voltage supply and the second voltage supply; 
 a second ESD clamp connected between the second node and the second voltage supply; and 
 a third ESD clamp connected between the fourth node and the second voltage supply. 
 
     
     
       13. The integrated circuit of  claim 12 , further comprising:
 a third ESD protection circuit coupled between the first node and the second voltage supply; and 
 a fourth ESD protection circuit coupled between the third node and the second voltage supply. 
 
     
     
       14. The integrated circuit of  claim 1 , further comprising:
 a second I/O pad, wherein the internal circuit is connected to the second I/O pad at a third node; and 
 a second ESD protection circuit connected between the second node and the third node. 
 
     
     
       15. The integrated circuit of  claim 14 , further comprising:
 a first ESD clamp connected between the first voltage supply and the second voltage supply; and 
 a second ESD clamp connected between the second node and the second voltage supply. 
 
     
     
       16. The integrated circuit of  claim 1 , further comprising:
 a second internal circuit connected between the first voltage supply and the second voltage supply; 
 a second I/O pad, wherein the second internal circuit is connected to the second I/O pad at a third node; and 
 a second ESD protection circuit connected between the second node and the third node. 
 
     
     
       17. A method for protecting an integrated circuit from electrostatic discharge (ESD), the integrated circuit coupled to a first voltage supply, a second voltage supply, and an input-output (I/O) pad, the method comprising:
 reverse biasing an ESD protection circuit that is connected to the I/O pad and the integrated circuit at a first node and coupled to a third voltage supply through an inductor at a second node; 
 discharging an ESD current present on the I/O pad through the ESD protection circuit; and 
 transferring the ESD current from the ESD protection circuit to an ESD clamp, wherein the ESD clamp transfers the ESD current away from the third voltage supply. 
 
     
     
       18. The method of  claim 17 , wherein the step of reverse biasing the ESD protection circuit reduces the parasitic capacitance of the ESD protection circuit. 
     
     
       19. The method of  claim 17 , wherein the step of reverse biasing the ESD protection circuit comprises tuning the inductor to have a relatively low impedance when a signal with a relatively low frequency is present on the I/O pad. 
     
     
       20. The method of  claim 17 , wherein the step of reverse biasing the ESD protection circuit comprises tuning the inductor to have a relatively high impedance when a signal with a relatively high frequency is present on the I/O pad.