Method for fabricating thin film transistor array substrate and thin film transistor array substrate

Abstract

After forming a gate electrode ( 4 a ) in a first step, a gate insulating film ( 5 ), a semiconductor film ( 8 ) and a conducting film ( 12 ) including a transparent conducting film ( 9 ) are stacked, and on the thus obtained multilayered body ( 18 ), a resist pattern ( 13 a ) including a first opening ( 14 a ) for exposing the conducting film ( 12 ) therein and a second opening ( 14 b ) having a bottom portion (B) above the gate electrode ( 4 a ) is formed. Portions of the conducting film ( 12 ) and the semiconductor film ( 8 ) exposed in the first opening ( 14 a ) are etched, the bottom portion (B) of the second opening ( 14 b ) is removed for exposing the conducting film ( 12 ) therein, and the exposed conducting film ( 12 ) is etched, so as to form a TFT ( 20 ) in a second step. A pixel electrode ( 5 a ), a protection masking layer ( 17 a ) and a projection ( 17 b ) are formed in a third step.

1. A method for fabricating a thin film transistor array substrate including a plurality of pixels provided on a substrate; a plurality of thin film transistors corresponding to the plurality of pixels and each thin film transistor including a gate electrode, a source electrode, a drain electrode and a semiconductor layer having a channel portion; a source line connected to the source electrode; a pixel electrode connected to the drain electrode for applying a voltage through a liquid crystal layer including liquid crystal molecules; and a projection provided over the pixel electrode for controlling orientation of the liquid crystal molecules, comprising:
 a first step of forming a pattern comprising the gate electrode on the substrate by photolithography; 
 a second step of forming a pattern comprising the thin film transistors including forming a multilayered body by stacking, on the substrate where the gate electrode has been formed, a gate insulating film, a semiconductor film to be made into the semiconductor layer and a conducting film including a transparent conducting film and covering the semiconductor film, and patterning the multilayered body by photolithography; and 
 a third step including forming a protection layer covering the thin film transistors, forming the projection by patterning at least the protection layer, and forming the pixel electrode by exposing a part of the transparent conducting film by photolithography, 
 the second step including a resist pattern forming procedure for forming a resist film covering the multilayered body, and forming, in the resist film, a first opening exposing the conducting film therein and disposed above a portion other than a region where the channel portion, the source line, the source electrode and the drain electrode are formed, and a second opening having a bottom portion with a given thickness and disposed above a portion of the multilayered body corresponding to the channel portion, so that when the first and second openings are formed in the resist film the first opening extends all the way through the resist film to expose the conducting film but the second opening does not extend all the way through the resist film; a first etching procedure for etching the conducting film exposed in the first opening and the semiconductor film disposed beneath the conducting film; and after the first etching procedure a second etching procedure for removing the bottom portion of the second opening to expose the conducting film and for etching the conducting film exposed therein. 
 
     
     
       2. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the conducting film has a masking property, and a portion of the conducting film disposed inside the periphery of the drain electrode is etched in the third step. 
     
     
       3. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the semiconductor film includes an upper first semiconductor film and a lower second semiconductor film, and the exposed conducting film and the first semiconductor film are etched in the second etching procedure. 
     
     
       4. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein a masking layer is formed as an upper layer or a lower layer of the protection layer, and the masking layer is formed simultaneously with the protection layer in the third step. 
     
     
       5. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the protection layer is made of a material with a masking property. 
     
     
       6. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the gate electrode is made of a first metal laminated film including a plurality of metal films stacked on one another, and the first metal laminated film includes a metal film made of an aluminum film or an aluminum alloy film. 
     
     
       7. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the conducting film includes a single layer of the transparent conducting film. 
     
     
       8. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the conducting film includes the transparent conducting film made of a compound of indium oxide and tin oxide, and a second metal laminated film covering the transparent conducting film and including a plurality of metal films stacked on one another, and
 the second metal laminated film includes a lower layer of a molybdenum film or a molybdenum alloy film and an upper layer of an aluminum film or an aluminum alloy film. 
 
     
     
       9. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein the semiconductor film is made of a material with higher transmissivity than amorphous silicon with the same thickness. 
     
     
       10. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein a plurality of gate lines each connected to the gate electrode and a gate line external leading electrode corresponding to an extended portion of each gate line are formed simultaneously with the gate electrode in the first step. 
     
     
       11. The method of fabricating a thin film transistor array substrate of  claim 10 , wherein the gate electrode, the gate line and the gate line external leading electrode are made of a first metal laminated film including a plurality of metal films stacked on one another, the first metal laminated film includes a titanium film or a titanium alloy film as a lowermost layer, and a portion of the titanium film or the titanium alloy film corresponding to the gate line external leading electrode is exposed by etching in the third step. 
     
     
       12. The method of fabricating a thin film transistor array substrate of  claim 11 , wherein the first metal laminated film includes the titanium film or the titanium alloy film as the lowermost layer, a metal film made of an aluminum film or an aluminum alloy film, and a molybdenum film or a molybdenum alloy film covering the metal film. 
     
     
       13. The method of fabricating a thin film transistor array substrate of  claim 10 , wherein the gate electrode, the gate line and the gate line external leading electrode are made of a first metal laminated film including a plurality of metal films stacked on one another, and the first metal laminated film includes a titanium film or a titanium alloy film as an uppermost layer. 
     
     
       14. The method of fabricating a thin film transistor array substrate of  claim 13 , wherein the first metal laminated film includes an aluminum film or an aluminum alloy film, and portions of the protection layer and the gate insulating film disposed inside the periphery of the gate line external leading electrode are etched in the third step. 
     
     
       15. The method of fabricating a thin film transistor array substrate of  claim 10 , wherein the source line and a source line external leading electrode corresponding to an extended portion of the source line are formed along a direction crossing the plurality of gate lines simultaneously with the source electrode in the second step. 
     
     
       16. The method of fabricating a thin film transistor array substrate of  claim 15 , wherein the gate electrode, the gate line and the gate line external leading electrode are made of a first metal laminated film including a plurality of metal films stacked on one another, the source electrode, the source line and the source line external leading electrode are made of a second metal laminated film including a plurality of metal films stacked on one another, and at least uppermost layers of the first metal laminated film and the second metal laminated film are removed by etching in portions corresponding to the gate line external leading electrode and the source line external leading electrode in the third step. 
     
     
       17. The method of fabricating a thin film transistor array substrate of  claim 16 , wherein the uppermost layer of each of the first metal laminated film and the second metal laminated film is made of an aluminum film or an aluminum alloy film, or a multilayered film of a molybdenum film or a molybdenum alloy film stacked on an aluminum film or an aluminum alloy film. 
     
     
       18. The method of fabricating a thin film transistor array substrate of  claim 15 , wherein the protection layer has a masking property and covers the thin film transistors, the gate line and the source line. 
     
     
       19. The method of fabricating a thin film transistor array substrate of  claim 15 , wherein the gate line external leading electrode and the source line external leading electrode are exposed by forming one opening correspondingly to at least one of the gate line external leading electrode and the source line external leading electrode by etching. 
     
     
       20. The method of fabricating a thin film transistor array substrate of  claim 1 , wherein a protection film included in the protection layer and the gate insulating film are etched in portions outside the periphery of the drain electrode in the third step.