Thin film transistor array substrate and method for fabricating the same

Abstract

A TFT array substrate includes a gate line, a gate electrode, and a gate pad on a substrate, each of which including stacked layers of a first metal and a transparent conductive material, respectively, a pixel electrode formed of the transparent conductive material, a gate insulation layer on the substrate including the gate line and the gate electrode, the gate insulation layer having first and second open areas exposing the pixel electrode and the gate pad, a semiconductor layer formed on the gate insulation layer, a data line crossing the gate line to define a sub-pixel region, a source electrode diverging from the data line, a drain electrode spaced apart from the source electrode and connected to the pixel electrode, a data pad at an end of the data line; a masking layer covering the data line, the source electrode and the drain electrode, and an oxidation-prevention layer covering the gate pad and the data pad.

1. A method for fabricating a TFT array substrate, comprising: sequentially depositing a first metal layer and a transparent conductive layer on a substrate; forming a gate line, a gate electrode, a gate pad and a pixel electrode by patterning the first metal layer and the transparent conductive layer using a first mask; depositing an insulation layer, an amorphous silicon layer and a second metal layer over the substrate; forming a semiconductor layer, a data line, a data pad, a first open area in a pixel region, and a second open area in the gate pad by patterning the amorphous silicon layer and the second metal layer using a second mask; depositing a conductive material over the substrate; forming first and second masking layers and first and second oxidation-prevention layers by patterning the conductive material using a third mask; forming source and drain electrodes by etching the second metal layer exposed between the first and second masking layers using the first and second masking layers as a mask to define a channel region; and exposing the transparent conductive layer of the pixel electrode by etching the first metal layer exposed through the first open area, and wherein the first and second open areas are formed by patterning the insulation layer, the amorphous silicon layer and the second metal layer using the second mask, wherein the first masking layer covers the data line and the source electrode, wherein the second masking layer covers the drain electrode and a portion of the first metal layer of the first open area, and connects the drain electrode to the pixel electrode, and wherein the first metal of the first open area contacts the insulation layer under the drain electrode, and wherein the first and second oxidation-prevention layers respectively cover the gate pad and the data pad. 
     
     
       2. The method of  claim 1 , further comprising treating a surface of the semiconductor layer in the channel region with O 2  plasma, after the step of forming source and drain electrodes. 
     
     
       3. The method of  claim 1 , wherein the etching of each of the first and second metal layers includes a wet-etching process. 
     
     
       4. The method of  claim 3 , wherein the first metal layer includes one of aluminum, aluminum neodymium and copper, and the second metal layer includes one of molybdenum and molybdenum alloy. 
     
     
       5. The method of  claim 1 , wherein the first and second masking layers and the first and second oxidation-prevention layers are formed of a metal layer,
 wherein the metal layer is titanium or titanium alloy. 
 
     
     
       6. The method of  claim 1 , wherein the step of forming the gate line, the gate electrode, the gate pad and the pixel electrode further comprising: forming a lower capacitor electrode, and
 wherein the step forming the semiconductor layer, the data line, the data pad, and the first and second open areas further comprising: forming an upper capacitor electrode overlapping the lower capacitor electrode. 
 
     
     
       7. The method of  claim 6 , wherein the insulation layer and the amorphous silicon layer are formed between the lower capacitor electrode and the upper capacitor electrode. 
     
     
       8. The method of  claim 7 , wherein the step of forming first and second masking layers and first and second oxidation-prevention layers further comprising: forming a third masking layer on the upper capacitor electrode to connect the upper capacitor electrode to the pixel electrode. 
     
     
       9. The method of  claim 1 , wherein the first masking layer formed on the data line is integrally formed with the second oxidation-prevention layer on the data pad as a single body. 
     
     
       10. The method of  claim 1 , wherein the second mask includes a diffraction exposure mask. 
     
     
       11. The method of  claim 1 , wherein the step of forming the semiconductor layer, the data line, the data pad, and the first and second open areas further comprising:
 forming a photoresist layer having a step coverage on the second metal layer by using the second mask; 
 forming the first and second open areas by removing the staked layer of the insulation layer, the amorphous silicon layer and the second metal layer selectively in state of using the photoresist layer as a mask; 
 removing a thinner portion of the photoresist layer by an ashing process; and 
 forming the semiconductor layer, the data line, and the data pad by etching the amorphous silicon layer and the second metal layer using the ashed photoresist layer as a mask. 
 
     
     
       12. The method of  claim 11 , wherein the insulation layer, the amorphous silicon layer and the second metal layer are etched together in a dry-etching method. 
     
     
       13. The method of  claim 1 , wherein the pixel electrode is formed in the entire area of the sub-pixel region.