Capacitive integrate and fold charge-to-digital converter

Abstract

A circuit for converting a charge signal into a binary format of output bits comprises: an integration circuit including an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between the inverting input terminal and the output terminal, the integrating capacitor for storing a charge input selectively provided by a sensor diode; and a folding circuit having a fold capacitor, the fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input.

1. A charge to digital converter comprising:
 an integration circuit comprising an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between said inverting input terminal and said output terminal, said integrating capacitor for storing a charge input selectively provided by a sensor diode; and 
 a folding circuit having a fold capacitor, said fold capacitor switchably coupled to a fold voltage source via a fold buffer for charging said fold capacitor to a predetermined fold charge value when said integrating capacitor stores said charge input selectively provided by the sensor diode, and said fold capacitor switchably decoupled from the fold voltage source and coupled to said integrating capacitor for selectively removing at least a portion of said stored charge input when said stored charge input exceeds a predetermined integration charge value. 
 
     
     
       2. The converter of  claim 1  wherein said folding circuit further comprises said fold buffer disposed between said fold voltage source and said fold capacitor. 
     
     
       3. The converter of  claim 1  further comprising a residue quantizing circuit coupled to said output terminal of said operational transconductance amplifier, said residue quantizing circuit providing at least one additional digital bit to a digital output signal, said at least one additional bit corresponding to a residual charge in said integrating capacitor. 
     
     
       4. The converter of  claim 1  further comprising a voltage comparator and a fold logic circuit connected to an output of said voltage comparator, said voltage comparator having an input connected to said output terminal of said operational transconductance amplifier. 
     
     
       5. The converter of  claim 4  wherein said fold logic circuit functions to selectively remove stored charge from said integrating capacitor when said stored charge exceeds said predetermined integration charge value. 
     
     
       6. The converter of  claim 5  wherein said predetermined integration charge value is a function of a rate of removal of said stored charge from said integrating capacitor. 
     
     
       7. The converter of  claim 1  wherein said folding circuit comprises a plurality of buffer compensation capacitors, each said buffer compensation capacitor having one end coupled to ground and another end switchably connected to an output of said fold buffer. 
     
     
       8. The converter of  claim 1  further comprising a sensor input switch disposed between said integrating capacitor and said sensor diode. 
     
     
       9. A method of converting a charge input to a digital signal output, said method comprising the steps of:
 charging an integrating capacitor to a predetermined integration charge value with the charge input; 
 charging a fold capacitor to a predetermined fold charge level with a fold voltage source; 
 transferring charge between said integrating capacitor and said fold capacitor for a predetermined transfer time interval; and 
 producing said digital signal output as a function of charge transferred by tracking said charge transferal via a fold logic circuit. 
 
     
     
       10. The method of  claim 9  wherein said step of transferring said charge comprises a step of operating a fold switch connected to the fold capacitor. 
     
     
       11. The method of  claim 10  wherein said step of operating said fold switch is controlled by said fold logic circuit. 
     
     
       12. A multi-channel charge to digital converter comprising:
 a voltage divider; 
 a plurality of converter channels; and 
 a fold buffer coupled to said voltage divider, said fold buffer switchably connected to each of said converter channels, 
 wherein at least one of said converter channel comprises:
 an integration circuit comprising an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between said inverting input terminal and said output terminal, said integrating capacitor for storing a charge input selectively provided by a sensor diode; and 
 a folding circuit having a fold capacitor, said fold capacitor switchably coupled to said fold buffer for charging said fold capacitor to a predetermined fold charge value when said integrating capacitor stores said charge input selectively provided by the sensor diode, and said fold capacitor switchably decoupled from the fold buffer and coupled to said integrating capacitor for selectively receiving at least a portion of said stored charge input when said stored charge input exceeds a predetermined integration charge value. 
 
 
     
     
       13. The converter of  claim 12  wherein said folding circuit further comprises a charge switch pair for switchably connecting said folding capacitor to said fold buffer. 
     
     
       14. The converter of  claim 12  further comprising a second fold buffer, said fold capacitor switchably coupled to either said fold buffer or said second fold buffer. 
     
     
       15. The converter of  claim 14  further comprising a second integrator circuit including a second operational transconductance amplifier, an inverting input terminal of said second operational transconductance amplifier coupled to said output terminal of said operational transconductance amplifier in said integration circuit.