Semiconductor device and semiconductor memory device

Abstract

A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.

1. A semiconductor device, comprising:
 a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface; 
 a first element group including a plurality of first semiconductor elements with first electrode pads arranged along one outline side, the first semiconductor elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the first electrode pads exposed; 
 a second element group including a plurality of second semiconductor elements with second electrode pads arranged along one outline side, the second semiconductor elements being stacked in a step-like shape on the first element group with the outline sides directed to the same direction and the second electrode pads exposed; 
 first metallic wires electrically connecting the first electrode pads and the connection pads of the wiring board; 
 second metallic wires electrically connecting the second electrode pads and the connection pads of the wiring board; and 
 a sealing resin layer formed on the first surface of the wiring board to seal the first and second element groups together with the first and second metallic wires, 
 wherein the lowermost semiconductor element among the second semiconductor elements has a thickness larger than those of the other semiconductor elements among the second semiconductor elements, and 
 wherein the second electrode pads are arranged on opposite sides of the second semiconductor elements from the wiring board, and a hollow portion is arranged below the lowermost semiconductor element among the second semiconductor elements corresponding to the second electrode pads of the lowermost semiconductor element. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the second element group satisfies conditions T 1 >T 2 , T 1 =50 to 150 μm and T 2 =10 to 50 μm, where T 1  is a thickness of the lowermost semiconductor element, and T 2  is a thickness of the other semiconductor element. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein the first element group satisfies conditions T 3 >T 4 , T 3 =50 to 150 μm and T 4 =10 to 50 μm, where T 3  is a thickness of the lowermost semiconductor element among the first semiconductor elements, and T 4  is a thickness of the other semiconductor element among the first semiconductor elements. 
 
     
     
       4. The semiconductor device according to  claim 1 ,
 wherein the first element group has four or more of the first semiconductor elements, and the second element group has four or more of the second semiconductor elements. 
 
     
     
       5. The semiconductor device according to  claim 1 ,
 wherein the first element group has a plurality of semiconductor memory elements as the first semiconductor elements, and the second element group has a plurality of semiconductor memory elements as the second semiconductor elements. 
 
     
     
       6. The semiconductor device according to  claim 5 , further comprising:
 a controller element, stacked on the second element group, having electrode pads arranged along at least one outline side; and 
 third metallic wires electrically connecting the electrode pads of the controller element and the connection pads of the wiring board. 
 
     
     
       7. The semiconductor device according to  claim 5 , further comprising:
 external connection terminals formed on the second surface of the wiring board. 
 
     
     
       8. A semiconductor device, comprising:
 a wiring board having a first surface provided with an element mounting section and connection pads, and a second surface on a side opposite to the first surface; 
 a first element group including a plurality of first semiconductor elements with first electrode pads arranged along one outline side, the first semiconductor elements being stacked in a step-like shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the first electrode pads exposed; 
 a second element group including a plurality of second semiconductor elements with second electrode pads arranged along one outline side, the second semiconductor elements being stacked in a step-like shape on the first element group with the outline sides directed to the same direction and the second electrode pads exposed; 
 first metallic wires electrically connecting the first electrode pads and the connection pads of the wiring board; 
 second metallic wires electrically connecting the second electrode pads and the connection pads of the wiring board; and 
 a sealing resin layer formed on the first surface of the wiring board to seal the first and second element groups together with the first and second metallic wires, 
 wherein the second electrode pads are arranged on opposite sides of the second semiconductor elements from the wiring board, a hollow portion is arranged below the lowermost semiconductor element among the second semiconductor elements corresponding to the second electrode pads of the lowermost semiconductor element, and the second element group is disposed on the first element group via a spacer layer. 
 
     
     
       9. The semiconductor device according to  claim 8 ,
 wherein the spacer layer includes an insulating resin layer which also serves as an adhesive layer. 
 
     
     
       10. The semiconductor device according to  claim 8 ,
 wherein the spacer layer has a thickness larger than those of the first semiconductor elements. 
 
     
     
       11. The semiconductor device according to  claim 8 ,
 wherein the spacer layer has a thickness larger than those of the second semiconductor elements. 
 
     
     
       12. The semiconductor device according to  claim 9 ,
 wherein ends of the first metallic wires, which are connected to the uppermost semiconductor element among the first semiconductor elements, are buried in the insulating resin layer. 
 
     
     
       13. The semiconductor device according to  claim 8 ,
 wherein the first element group has four or more of the first semiconductor elements, and the second element group has four or more of the second semiconductor elements. 
 
     
     
       14. The semiconductor device according to  claim 8 ,
 wherein the first element group has a plurality of semiconductor memory elements as the first semiconductor elements, and the second element group has a plurality of semiconductor memory elements as the second semiconductor elements. 
 
     
     
       15. The semiconductor device according to  claim 14 , further comprising:
 a controller element, stacked on the second element group, having electrode pads arranged along at least one outline side; and 
 third metallic wires electrically connecting the electrode pads of the controller element and the connection pads of the wiring board. 
 
     
     
       16. The semiconductor device according to  claim 14 , further comprising:
 external connection terminals formed on the second surface of the wiring board.