Molecular wire crossbar logic (MWCL)

Abstract

A programmable logic array (PLA) comprising a two-dimensional array of a plurality of nanometer-scale switches is provided. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. A plurality of switches is configurable as an AND gate and a plurality of switches is configurable as an OR gate.

1. A programmable logic array comprising a two-dimensional array of a plurality of crossed-wire devices, each device comprising a junction formed by a pair of crossed wires where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction, said junction having a functional dimension in nanometers and said at least one connector species comprising a bi-stable molecule, wherein a plurality of connector species is configurable as an AND gate and a plurality of connector species is configurable as an OR gate. 
     
     
       2. The programmable logic array of  claim 1  wherein said junction forms an asymmetric non-linear resistor. 
     
     
       3. The programmable logic array of  claim 1  wherein said junction forms a diode. 
     
     
       4. The programmable logic array of  claim 1  wherein said junction has a state that is altered by application of a voltage. 
     
     
       5. The programmable logic array of  claim 1  wherein said junction is a singly configurable or reconfigurable one connector species. 
     
     
       6. The programmable logic array of  claim 1  wherein at least one of said two wires has a thickness that is about the same size as said at least one connector species, and over an order of magnitude longer than its diameter. 
     
     
       7. The programmable logic array of  claim 6  wherein both of said two wires have a thickness that is about the same size as said at least one connector species. 
     
     
       8. The programmable logic array of  claim 1  wherein both of said two wires have a thickness that ranges from sub-micrometer to micrometer. 
     
     
       9. The programmable logic programmable logic array of  claim 1  comprising a plurality of AND gates and a plurality of OR gates. 
     
     
       10. The programmable logic array of  claim 9  wherein said plurality of AND gates is followed by said plurality of OR gates. 
     
     
       11. The programmable logic array of  claim 9  wherein said plurality of OR gates is followed by said plurality of AND gates. 
     
     
       12. The programmable logic array of  claim 1  wherein each said wire independently comprises a conductor or a semiconductor. 
     
     
       13. The programmable logic array of  claim 12  further including an insulating layer or a modulation-doped coating on at least one of said wires. 
     
     
       14. The programmable logic array of  claim 13  wherein said insulating layer comprises an oxide. 
     
     
       15. The programmable logic array of  claim 12  wherein said semiconductor is internally doped. 
     
     
       16. A method of fabricating a programmable logic array comprising a two-dimensional array of a plurality of crossed-wire devices, each device comprising a junction formed by a pair of crossed wires where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction, said junction having a functional dimension in nanometers and said at least one connector species comprising a bi-stable molecule, wherein a plurality of connector species is configurable as an AND gate and a plurality of connector species is configurable as an OR gate, said method comprising (a) forming a first set of wires comprising a plurality of said first wires, (b) depositing said connector species over at least a portion of said first set of wires, (c) forming a second set of wires comprising a plurality of said second wires over said first set of wires so as to form said junction at each place where a second said wire crosses a first said wire, (d) configuring a first plurality of said connector species as an AND gate, and (e) configuring a second plurality of said connector species as an OR gate. 
     
     
       17. The method of  claim 16  wherein said junction forms an asymmetric non-linear resistor. 
     
     
       18. The method of  claim 16  wherein said junction forms a diode. 
     
     
       19. The method of  claim 16  wherein said junction has a state that is altered by application of a voltage. 
     
     
       20. The method of  claim 16  wherein said junction is a singly configurable or reconfigurable one connector species. 
     
     
       21. The method of  claim 16  wherein at least one of said two wires has a thickness that is about the same size as said at least one connector species, and over an order of magnitude longer than its diameter. 
     
     
       22. The method of  claim 21  wherein both of said two wires have a thickness that is about the same size as said at least one connector species. 
     
     
       23. The method of  claim 16  wherein both of said two wires have a thickness that ranges from sub-micrometer to micrometer. 
     
     
       24. The method of  claim 16  comprising a plurality of AND gates and a plurality of OR gates. 
     
     
       25. The method of  claim 24  wherein said plurality of AND gates is followed by said plurality of OR gates. 
     
     
       26. The method of  claim 24  wherein said plurality of OR gates is followed by said plurality of AND gates. 
     
     
       27. The method of  claim 16  wherein each said wire independently comprises a conductor or a semiconductor. 
     
     
       28. The method of  claim 27  further including forming an insulating layer or a modulation-doped coating on at least one of said wires. 
     
     
       29. The method of  claim 28  wherein said insulating layer comprises an oxide. 
     
     
       30. The method of  claim 27  wherein said semiconductor is internally doped.