Thin film transistor array substrate and manufacturing method thereof

Abstract

A thin film transistor (TFT) array substrate for a liquid crystal display comprises a gate line and a data line formed in a display region, a gate connecting line and a data connecting line formed in a PAD region, and a TFT formed at an intersection between the gate line and the data line. The TFT comprises a gate electrode on a base substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a doped semiconductor layer on the semiconductor layer, and a source electrode and a drain electrode that are on the doped semiconductor layer, and a TFT channel is defined in the semiconductor layer between the source electrode and the drain electrode. The array substrate further comprises a passivation layer that is formed on the source electrode and the drain electrode and a pixel electrode, a portion of which is formed under the drain electrode and connected with the drain electrode.

1. A thin film transistor (TFT) array substrate for a liquid crystal display, comprising:
 a gate line and a data line formed in a display region, 
 a gate connecting line and a data connecting line formed in a PAD region, 
 a TFT formed at an intersection between the gate line and the data line, wherein the TFT comprises a gate electrode on a base substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a doped semiconductor layer on the semiconductor layer, and a source electrode and a drain electrode that are on the doped semiconductor layer, and a TFT channel is defined in the semiconductor layer between the source electrode and the drain electrode; 
 a passivation layer that is formed on the source electrode and the drain electrode; and 
 a pixel electrode, which is formed outside of the stacked layers of the semiconductor layer and the doped semiconductor layer and a portion of which is formed under the drain electrode and connected with the drain electrode. 
 
     
     
       2. The TFT array substrate for a liquid crystal display of  claims 1 , wherein the pixel electrode is formed on the gate insulating layer. 
     
     
       3. The TFT array substrate for a liquid crystal display of  claims 1 , wherein the pixel electrode is formed on the base substrate. 
     
     
       4. A method of manufacturing a thin film transistor (TFT) array substrate for a liquid crystal display, comprising the steps of:
 (1) depositing a gate metal layer on a base substrate and forming a pattern of a gate electrode and a gate line in a display region and a pattern of a gate connecting line in a gate line PAD region through a first patterning process; 
 (2) depositing sequentially a gate insulation layer, a semiconductor layer and a doped semiconductor layer on the base substrate after step 1 and forming patterns of a gate insulation layer, a semiconductor layer and a doped semiconductor layer on the gate line and the gate electrode in the display region through a second patterning process; 
 (3) depositing a transparent conductive layer on the base substrate after step 2 and forming a pattern of a pixel electrode by a third patterning process by patterning the transparent conductive layer; and 
 (4) depositing sequentially a source/drain metal layer and a passivation layer on the base substrate after step 3 having the pattern of the pixel electrode, forming patterns of a drain electrode, a source electrode, a data line and a TFT channel in the display region and forming a data connecting line in a data line PAD region through a fourth patterning process by patterning the stacked layers of the source/drain metal layer and the passivation layer, wherein the doped semiconductor layer in the TFT channel between the drain electrode and the source electrode is removed, the drain electrode is connected with the pixel electrode, the gate connecting line is exposed through a gate connecting line via hole in the gate line PAD region, and the data connecting line is exposed through a data connecting line via hole in the data line PAD region. 
 
     
     
       5. The manufacturing method of  claim 4 , wherein the step 2 comprises the steps of:
 (211) depositing sequentially the gate insulating layer, the semiconductor layer and the doped semiconductor layer on the base substrate after step 1; and 
 (212) etching the doped semiconductor layer and the semiconductor layer through the second patterning process so as to remove the semiconductor layer and the doped semiconductor layer in the gate line PAD region and the data line PAD region and form the patterns of the semiconductor layer and the doped semiconductor layer on the gate line and the gate electrode in the display region. 
 
     
     
       6. The manufacturing method of  claim 5 , wherein the step 3 comprises the steps of:
 (311) depositing the transparent conductive layer on the base substrate after step 2; and 
 (312) forming the pattern of the pixel electrode on the gate insulating layer through the third patterning process. 
 
     
     
       7. The manufacturing method of  claim 6 , wherein the step 4 comprises the steps of:
 (411) depositing sequentially the source/drain metal layer and the passivation layer on the base substrate after step 3; 
 (412) applying a layer of photoresist on the base substrate after step 411; 
 (413) patterning the photoresist with a gray tone mask so as to form a photoresist pattern that corresponds to the source electrode, the drain electrode, the data line, and the TFT channel in the display region, the data connecting line in the data line PAD region, and the gate connecting line in the gate line PAD region, wherein the photoresist pattern exposes the surface of the base substrate corresponding to the TFT channel, the pixel electrode, and the gate connecting line via hole and has a reduced thickness in a portion corresponding to the data connecting line via hole; 
 (414) etching the exposed passivation layer, the source/drain metal layer and the doped semiconductor layer by using the photoresist pattern as an etching mask, so that the patterns of the drain electrode, the source electrode, the data line and the TFT channel are formed in the display region, the drain electrode is connected with the pixel electrode, the pattern of the data connecting line is formed in the data line PAD region, and the exposed passivation layer and the source/drain metal layer is etched in the gate line PAD region to expose the gate insulating layer; 
 (415) thinning the layer of photoresist through a photoresist ashing process so as to remove the photoresist in the portion corresponding to the data connecting line via hole that exposes the passivation layer; 
 (416) etching the gate insulating layer in the gate line PAD region so as to form the gate connecting line via hole that exposes the gate connecting line and etching the passivation layer in the data line PAD region by using the remaining photoresist pattern so as to form the data connecting line via hole that exposes the data connecting line; and 
 (417) lifting off the remained photoresist through a photoresist lifting-off process. 
 
     
     
       8. The manufacturing method of  claim 6 , wherein the step 2 comprises the steps of:
 (221) depositing sequentially the gate insulating layer, the semiconductor layer and the doped semiconductor layer on the base substrate after step 1; and 
 (222) etching the doped semiconductor layer, the semiconductor layer and the gate insulating layer through the second patterning process so as to remove the semiconductor layer, the doped semiconductor layer and the gate insulating layer in the gate line PAD region and the data line PAD region and form the patterns of the semiconductor layer, the doped semiconductor layer and the gate insulating layer on the gate line and the gate electrode in the display region. 
 
     
     
       9. The manufacturing method of  claim 8 , wherein the step 3 comprises the steps of:
 (321) depositing the transparent conductive layer on the base substrate after step 2; and 
 (322) forming the pattern of the pixel electrode on the base substrate through the third patterning process. 
 
     
     
       10. The manufacturing method of  claim 9 , wherein the step 4 comprises the steps of:
 (421) depositing the source/drain metal layer and the passivation layer sequentially on the base substrate after step 3; 
 (422) applying a layer of photoresist on the base substrate after step 421; 
 (423) patterning the photoresist with a gray tone mask so as to form a photoresist pattern that corresponds to the source electrode, the drain electrode, the data line, and the TFT channel in the display region, the data connecting line in the data line PAD region, and the gate connecting line in the gate line PAD region, wherein the photoresist pattern exposes the surface of the base substrate corresponding to the TFT channel, the pixel electrode, and the gate connecting line via hole and has a reduced thickness in a portion corresponding to the data connecting line via hole; 
 (424) etching the exposed passivation layer, the source/drain metal layer and the doped semiconductor layer by using the photoresist pattern as an etching mask, so that the patterns of the drain electrode, the source electrode, the data line and the TFT channel are formed in the display region, the drain electrode is connected with the pixel electrode, the pattern of the data connecting line in the data line PAD region, and the exposed passivation layer and the source/drain metal layer in the gate line PAD region is etched so as to form the gate connecting line via hole that exposes the gate connecting line; 
 (425) thinning the layer of photoresist through a photoresist ashing process so as to remove the photoresist in the portion corresponding to the data connecting line via hole that exposes the passivation layer; 
 (426) etching the passivation layer in the data line PAD region by using the remaining photoresist pattern so as to form the data connecting line via hole that exposes the data connecting line; and 
 (427) lifting off the remained photoresist through a photoresist lifting-off process.