Method and circuit of high performance variable length coding and decoding for image compression

Abstract

The differential value of the adjacent pixels is calculated firstly and is coded by a VLC coding. The VLC coding includes codes representing the Quotient and Remainder with a marker bit inserted in between. The divider is predicted with no code in the coded data stream. If three pixel components are presented in the same clock time, three VLC encoders and three VLD decoders are applied to encode and decode one pixel at a time. During encoding, both Remainder and Quotient of the same pixel component are encoded in parallel followed. During decoding, both Remainder and Quotient of the same pixel component are decoded in parallel and the results of the first pixel component are used a reference to decode the second pixel component which adopts the same decoding procedure and the decoded results of the second pixel component is used as reference to decode the third pixel component.

1. A method of compressing pixel components, comprising:
 calculating differential values between adjacent pixels of a group of pixels within an image frame; 
 calculating and coding the value of quotient obtained from dividing one differential value by a predicted divisor; 
 calculating and coding, using a circuit, the value of remainder obtained from dividing said one differential value by the predicted divisor being represented by an integer number with the power of 2; 
 calculating next value of the predicted divisor by reference to current value of the predicted divisor wherein the value of the predicted divisor is adjusted dynamically during compression; and 
 using the next value of the predicted divisor to calculate and code the values of quotient and remainder for another differential value next said one differential value. 
 
     
     
       2. The method of  claim 1 , wherein at least one value of the divisor is the average of the last value of the predicted divisor and a previous differential value of adjacent pixels. 
     
     
       3. The method of  claim 1 , wherein the code of the quotient and a marker bit used to separate the code for the quotient and the code for the remainder use different polarity of a digital bit. 
     
     
       4. The method of  claim 1 , wherein a first predetermined value is assigned to be the predicted divisor of a pixel if the differential value of adjacent pixel is greater than a first threshold, a second predetermined value is assigned to be the predicted divisor of a pixel if the differential value of adjacent pixel is greater than a second threshold, and a third predetermined value is assigned to be the predicted divisor of a pixel if the differential value of adjacent pixel is greater than a third threshold. 
     
     
       5. The method of  claim 4 , wherein the quotient of a pixel component can be coded first, followed by the remainder of the same pixel component, or the remainder can be coded first, followed by the quotient. 
     
     
       6. The method of  claim 1 , wherein when the differential value between the next pixel and the previous pixel is larger than a predetermined threshold, the previous predicted divisor is used as the predicted divisor for coding the next pixel. 
     
     
       7. The method of  claim 1 , wherein the remainder is a binary code having the same bit number of the divisor which is an integer number of the power of 2. 
     
     
       8. A method of efficiently decompressing pixel components, comprising:
 fetching compressed pixel components which are stored in an image buffer; 
 applying a variable length decoding procedure including but not limited to the following steps: 
 calculating a remainder, using a circuit, of a first pixel component by referring to the current divisor and the calculated first quotient; 
 calculating a quotient of the first pixel component by referring to the current divisor and remainder; and 
 applying a decoded remainder and quotient to calculate a differential value of the adjacent pixel component and to determine a divisor value for the next pixel component; 
 re-aligning the compressed pixel component bit position and repeat the above variable length decoding procedure for recovering the second pixel component; and 
 if there is a third pixel component within the compressed pixels, then, realigning the compressed pixel component bit position and repeating a variable length decoding procedure for recovering the third pixel component. 
 
     
     
       9. The method of  claim 8 , wherein the value of the predicted divisor of the power of 2 is assigned to represent the number of bits of the remainder. 
     
     
       10. The method of  claim 8 , wherein the remainder and the quotient of the first pixel component are decoded in parallel, followed by the remainder and the quotient of the second pixel component which are also decoded in parallel and if available, followed by the remainder and quotient of the third pixel component which are decoded in parallel. 
     
     
       11. The method of  claim 8 , wherein the quotient of the first pixel component is decoded first followed by the remainder of the first pixel component, then, the quotient of the second pixel component is decoded and followed by the remainder of the second pixel component, and if the third component is available, the quotient of the first pixel component is decoded, then followed by the remainder of the third pixel component. 
     
     
       12. The method of  claim 8 , wherein the decoded quotient and the previous divisor are used to calculate the divisor of the next pixel. 
     
     
       13. The method of  claim 8 , wherein decoding the quotient and the remainder of a pixel components and updating the divisors of the next pixel components are completed in a fixed clock cycle time. 
     
     
       14. The method of  claim 8 , wherein at least two levels of decoding procedure is applied to decode the quotient value of each pixel component. 
     
     
       15. An apparatus for efficiently decompressing differential value of adjacent pixels, comprising:
 a loader accessing and storing compressed pixel data into a temporary storage device and fetching the compressed data for decoding; 
 at least a circuit decompressing a first pixel component comprising the following circuits: 
 a first VLD decoder decoding a quotient and another VLD decoder decoding a remainder of the differential value of the first pixel component with these two decoders decoding the quotient and remainder in parallel based on a current divisor; 
 a calculator with input of a decoded quotient and a remainder from the first VLD decoder, calculating the value of the differential value of the first pixel component, and then calculating a divisor of the next pixel; and 
 a shifter shifting out a decoded quotient, marker and remainder bits and feeding shifted bits into the next circuit for decoding the next pixel component; 
 a second decoding circuit with the input from the shifted bits of the compressed pixel component, if the second pixel component is available in the same clock cycle with the first pixel component, going through the same decoding procedure as for the first pixel component; and 
 a third decoding circuit with the input from the shifted bits of the compressed pixel component, if the third pixel component is available in the same clock cycle with the first pixel component, going through the same decoding procedure as for the first pixel component. 
 
     
     
       16. The apparatus of  claim 15 , wherein the remainder and quotient are decoded in parallel, and the decoded remainder and quotient are used to decode the differential value of the adjacent pixels which is used to calculate the predicted divisor for the next pixel. 
     
     
       17. The apparatus of  claim 15 , wherein the decoded first pixel component is used as a reference to decode the second pixel component, and the decoded second pixel component is used as a reference to decode the third pixel component. 
     
     
       18. The apparatus of  claim 15 , wherein a quotient decoder with two levels of logic gates of decoding is applied to calculate the quotient of the differential value.