Computer automated method for manufacturing an integrated circuit pattern layout

Abstract

A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.

1. A method of manufacturing an integrated circuit comprising:
 designing layout information including patterns of cells, wires, and vias to be placed on a semiconductor substrate implemented in a graphic image space of a chip area; 
 verifying the layout information in the graphic image space by placing a plurality of marks on each of contours of the patterns, allocating selectively a plurality of discrete areas in a same level with the patterns on the marks taking account of an influence of the optical proximity effect of the patterns, merging adjacent discrete areas overlapping each other into a single polygon so as to define a plurality of isolated groups by the polygon, sorting the marks into the isolated groups so that the adjacent marks are merged in a same group, determining a candidate hot spot by counting a total number of the marks included in each of the isolated groups, extracting a group with the total number of the marks more than a predetermined value, and modifying a corresponding pattern in the candidate hot spot; 
 modifying the layout information by executing a lithography rule check; 
 producing a plurality of masks based on modified layout information; 
 forming an insulating film on the semiconductor substrate; 
 selectively etching a part of the insulating film by using one of the masks; and forming corresponding actual vias and corresponding actual wires, using the modified layout information, connected to the actual vias in the insulating film. 
 
     
     
       2. The method of  claim 1 , wherein designing the layout information includes placing patterns including logical cells, high-yield cells, wires, single vias, and multicut vias implemented in the graphic image space of the chip area. 
     
     
       3. The method of  claim 1 , wherein verifying the layout information further comprises placing an additional mark on one of the contours based on additional mark information before sorting the marks. 
     
     
       4. The method of  claim 1 , wherein each of the patterns are defined by a rectangular regions, and placing the marks includes:
 placing the marks on respective vertices of each of the rectangular regions. 
 
     
     
       5. The method of  claim 1 , wherein modifying the layout includes:
 separating adjacent patterns apart so that the total number of the marks in the candidate hot spot is reduced. 
 
     
     
       6. The method of  claim 5 , wherein designing the layout information includes placing patterns including one or more patterns of logical cells, high-yield cells, wires, single vias, and/or multicut vias implemented in the graphic image space of the chip area. 
     
     
       7. The method of  claim 6 , wherein modifying the layout includes separating the adjacent patterns apart so that a total number of marks in the candidate hot spot is reduced. 
     
     
       8. The method of  claim 5 , wherein verifying the layout information further comprises placing an additional mark on one of the contours based on additional mark information before sorting the marks. 
     
     
       9. The method of  claim 5 , wherein each of the patterns are defined by a rectangular regions, and placing the mark includes placing the marks on respective vertices of each of the rectangular regions. 
     
     
       10. The method of  claim 5 , wherein designing the layout information includes replacing the vias with multiple via cells based on information of a multiple via cell library. 
     
     
       11. The method of  claim 5 , wherein designing the layout information includes expanding a routing space of the wires based on routing space information. 
     
     
       12. The method of  claim 5 , wherein designing the layout information includes folding the wires and expanding a routing space of the wires. 
     
     
       13. The method of  claim 1 , wherein designing the layout information includes replacing the vias with multiple via cells based on information of a multiple via cell library. 
     
     
       14. The method of  claim 13 , wherein verifying the layout information includes placing the marks on contours of the multiple via cells. 
     
     
       15. The method of  claim 1 , wherein designing the layout information includes expanding a routing space of the wires based on routing space information. 
     
     
       16. The method of  claim 15 , wherein verifying the layout information includes placing the marks on contours of wires after the routing space is expanded. 
     
     
       17. The method of  claim 1 , wherein designing the layout information includes folding the wires and expanding a routing space of the wires. 
     
     
       18. The method of  claim 17 , wherein verifying the layout information includes placing the marks on contours of the wires after the routing space is expanded. 
     
     
       19. The method of  claim 1 , wherein verifying the layout information further comprises allocating a plurality of areas on the marks taking account of an influence of an optical proximity effect before dividing the marks. 
     
     
       20. The method of  claim 19 , wherein verifying the layout information further comprises merging adjacent areas overlapping each other into a single polygon.