Semiconductor device and method of fabricating the same

Abstract

In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

1. A semiconductor device comprising a first MIS transistor of a first conductivity type and a second MIS transistor of the first conductivity type on a semiconductor substrate,
 the first MIS transistor including:
 a first gate insulation film on the semiconductor substrate in a first region, 
 a first gate electrode on the first gate insulation film, 
 a first channel region of a second conductivity type in the first region, the first channel region having a retrograde channel structure, and 
 a first extension region of the first conductivity type below side of the first gate electrode in the first region, and 
 
 the second MIS transistor including:
 a second gate insulation film on the semiconductor substrate in a second region, 
 a second gate electrode on the second gate insulation film, 
 a second channel region of the second conductivity type in the second region, the second channel region having a surface channel structure, and 
 a second extension region of the first conductivity type below side of the second gate electrode in the second region. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein
 the first MIS transistor further includes:
 a first side-wall spacer on a side surface of the first gate electrode; and 
 a first source/drain region of the first conductivity type below side of the first side-wall spacer in the first region, and 
 
 the second MIS transistor further includes:
 a second side-wall spacer on a side surface of the second gate electrode; and 
 a second source/drain region of the first conductivity type below side of the second side-wall spacer in the second region. 
 
 
     
     
       3. The semiconductor device of  claim 1 , wherein
 the second gate insulation film has the same film thickness as that of the first gate insulation film. 
 
     
     
       4. The semiconductor device of  claim 3 , wherein
 the first channel region and the second channel region each contain only a first impurity in terms of an impurity species. 
 
     
     
       5. The semiconductor device of  claim 3 , further comprising a third MIS transistor of the first conductivity type on the semiconductor substrate, the third MIS transistor including:
 a third gate insulation film on the semiconductor substrate in a third region, the third gate insulation film having a film thickness greater than those of the first gate insulation film and the second gate insulation film; 
 a third gate electrode on the third gate insulation film; and 
 a third channel region of the second conductivity type in the third region, the third channel region having a surface channel structure. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein
 the first channel region, the second channel region, and the third channel region each contain only a first impurity in terms of an impurity species. 
 
     
     
       7. The semiconductor device of  claim 5 , wherein
 the first MIS transistor is a transistor constituting an SRAM, 
 the second MIS transistor is a transistor constituting a logic circuit, and 
 the third MIS transistor is a transistor constituting an I/O circuit. 
 
     
     
       8. The semiconductor device of  claim 5 , wherein
 a drive voltage of the third MIS transistor is higher than a drive voltage of the first MIS transistor and a drive voltage of the second MIS transistor. 
 
     
     
       9. The semiconductor device of  claim 1 , wherein
 the first MIS transistor is a transistor constituting an SRAM. 
 
     
     
       10. The semiconductor device of  claim 1 , wherein
 the first gate insulation film and the second gate insulation film are made of a silicon oxynitride film. 
 
     
     
       11. The semiconductor device of  claim 1 , wherein
 a peak concentration of an impurity concentration of the first channel region is equal to or greater than 1×10 18 /cm 3 . 
 
     
     
       12. The semiconductor device of  claim 1 , wherein
 the second gate insulation film has a film thickness greater than that of the first gate insulation film. 
 
     
     
       13. The semiconductor device of  claim 12 , wherein
 the first channel region contains a first impurity and a second impurity which have the same conduction type, species of the first impurity and the second impurity being different from each other. 
 
     
     
       14. The semiconductor device of  claim 12 , wherein
 the first channel region contains a first impurity and a second impurity which have the same conduction type, species of the first impurity and the second impurity being different from each other, and 
 the second channel region contains only the first impurity in terms of the species. 
 
     
     
       15. The semiconductor device of  claim 12 , further comprising a third MIS transistor of the first conductivity type on the semiconductor substrate, the third MIS transistor including:
 a third gate insulation film on the semiconductor substrate in a third region, the third gate insulation film having the same film thickness as that of the first gate insulation film; 
 a third gate electrode on the third gate insulation film; and 
 a third channel region of the second conductivity type in the third region, the third channel region having a surface channel structure. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein
 the first channel region contains a first impurity and a second impurity which have the same conduction type, species of the first impurity and the second impurity being different from each other, and 
 the second channel region and the third channel region each contain only the first impurity in terms of the impurity species. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein
 the first impurity is boron, and 
 the second impurity is indium. 
 
     
     
       18. The semiconductor device of  claim 15 , wherein
 the first MIS transistor is a transistor constituting an SRAM, 
 the second MIS transistor is a transistor constituting an I/O circuit, and 
 the third MIS transistor is a transistor constituting a logic circuit. 
 
     
     
       19. The semiconductor device of  claim 15 , wherein
 a drive voltage of the second MIS transistor is higher than a drive voltage of the first MIS transistor and a drive voltage of the third MIS transistor.