Component comprising a thin-film transistor and CMOS-transistors and methods for production

Abstract

An electrical component, in the crystalline semiconductor body of which several CMOS transistors in high-voltage or low-voltage technology are formed. The individual CMOS transistors are separated from one another by insulation regions. On one insulation region, a thin-film transistor is formed, having a gate that is realized simultaneously with the gates of the CMOS transistors from the same polysilicon layer. The gate oxide of the thin-film transistor, just like a second polysilicon layer for source drain and body of the thin-film transistor, can be produced together with the structural elements already present in the CMOS process.

1. A semiconductor component comprising:
 a substrate that comprises a crystalline semiconductor body; 
 several CMOS transistors formed in the semiconductor body; 
 insulation regions formed between the CMOS transistors for mutual electrical isolation that comprise field oxide regions or STI regions; 
 an additional insulation region that has a larger surface area than the other insulation regions; 
 a thin-film transistor with a gate arranged on the additional insulation region; 
 a first polysilicon layer; and 
 a second polysilicon layer, 
 wherein both a gate of a CMOS transistor and a gate of the thin-film transistor are formed in the first polysilicon layer and therefore have the same layer thickness and crystal structure, 
 wherein the thin-film transistor has a source, a body and a drain that are formed in the second polysilicon layer, which also serves for structural elements of the CMOS transistors, and 
 wherein the source and drain of the thin-film transistor are formed on either side of the gate in the second polysilicon layer by a p + -type or n + -type doping. 
 
     
     
       2. A method for manufacturing a component with CMOS transistors and at least one thin-film transistor, comprising the steps of:
 electrically isolating the active regions for the CMOS transistors from one another in a semiconductor body by insulation regions by producing field oxide regions or STI regions, wherein at least one insulation region is formed, as a base for the at least one thin-film transistor, with a larger surface area than is necessary for pure insulation between the CMOS transistors; 
 producing, in the same common process, both the gate of the CMOS transistors above a layer of a gate dielectric and simultaneously the gate of the thin-film transistor on the flat insulation region by depositing and structuring a first polysilicon layer for a poly-1 level; 
 applying a second polysilicon layer, which overlaps the gate of the thin-film transistor and is structured into source, drain and body of the thin-film transistor, wherein structural elements of the poly-2 level of the CMOS transistor are simultaneously produced; and 
 forming a source and drain of the thin-film transistor on either side of the gate in the second polysilicon layer by a p + -type or n+-type doping. 
 
     
     
       3. The method according to  claim 2 , in which the first polysilicon layer is n + -doped after the deposition. 
     
     
       4. The method according to  claim 2 , in which a gate dielectric is produced above the gate of the thin-film transistor before the application of the second polysilicon layer. 
     
     
       5. The method according to  claim 2 , in which, from the layers for the first polysilicon layer, the gate dielectric and the second polysilicon layer, a capacitor using the two polysilicon layers as capacitor electrodes and the gate dielectric therebetween as the capacitor dielectric is produced at another point of the component. 
     
     
       6. The method according to  claim 2 , in which the second polysilicon layer is deposited undoped and in which a weak p-doping is subsequently produced therein. 
     
     
       7. The method according to  claim 6 , in which the weak p-doping is produced in the entire second polysilicon layer, the second polysilicon layer is finally highly doped to produce conductive structures in the designated areas of the CMOS transistors and said high doping is prevented in the area of the body by an absorber mask applied thereto. 
     
     
       8. The method according to  claim 6 , in which the weak p-doping in the body is produced with a doping level of 10 16 -10 17  cm −3 . 
     
     
       9. The method according to  claim 2 , in which, to produce the source and drain, both corresponding areas of the semiconductor body for the CMOS transistors and corresponding areas of the second polysilicon layer for the thin-film transistor are highly doped in a common step. 
     
     
       10. The method according to  claim 9 , in which a doping mask with mask openings for the source and drain is used for doping the source and drain of the thin-film transistor, wherein the gate and a reserve strip on either side of the gate are shielded from the doping. 
     
     
       11. The method according to  claim 10 , in which the high source and drain doping of the thin-film transistor is diffused in a thermal step into the area of the second polysilicon layer left undoped due to the reserve strip of the doping mask, and produces a doping gradient there. 
     
     
       12. The method according to  claim 11 , in which the doping gradient is produced by diffusion from the highly doped source and drain in a thermal step, with which the source and drain of the CMOS transistors are simultaneously activated. 
     
     
       13. The method according to  claim 2 , in which component structures of the CMOS transistors, selected from resistors, capacitor electrodes, electrical supply lines and field plates, are formed in the second polysilicon layer. 
     
     
       14. The method according to  claim 3 , in which the source and drain of the thin-film transistor are p + -doped, wherein an enhancement-type transistor with an accumulation channel is obtained. 
     
     
       15. The method according to  claim 3 , in which the source and drain of the thin-film transistor are n + -doped, wherein an enhancement-type transistor with an inversion channel is obtained.