Packet generation systems and methods

Abstract

Disclosed herein are various embodiments of methods, systems, and apparatus for increasing packet generation in a digital communication system. In one exemplary method embodiment, multiple input signals are interpolated, shifted, and aggregated into a composite signal for transmission over a network.

1. A method comprising:
 obtaining, by a device, a plurality of signals, each of the plurality of signals comprising a plurality of modulated subcarriers and having an initial sample rate; 
 increasing a sample rate of each of the plurality of signals by a factor equal to a number of signals in the plurality of signals to produce a plurality of increased sample rate signals; 
 shifting two or more of the plurality of increased sample rate signals in frequency by a multiple of the initial sample rate to produce two or more frequency-shifted increased sample rate signals, wherein the shifting is dependent upon whether the plurality of signals constitute an even number of signals or an odd number of signals; 
 combining the two or more frequency-shifted increased sample rate signals and any of the plurality of increased sample rate signals not subject to shifting to produce a combination signal; and 
 transmitting the combination signal from an antenna. 
 
     
     
       2. The method of  claim 1 , wherein the plurality of signals are obtained substantially simultaneously. 
     
     
       3. The method of  claim 1 , wherein the initial sample rate of each of the plurality of signals is 20MHz. 
     
     
       4. The method of  claim 3 , wherein increasing the sample rate of each of the plurality of signals comprises interpolating each of the plurality of signals by a factor corresponding to the number of signals in the plurality of signals. 
     
     
       5. The method of  claim 1 , wherein the increasing, the shifting and the combining is performed by at least one of a digital signal processor (DSP), a microprocessor, a general purpose processor, or an application specific integrated circuit. 
     
     
       6. The method of  claim 1 , wherein increasing the sample rate comprises interpolating each of the plurality of signals. 
     
     
       7. The method of  claim 6 , wherein each of the plurality of signals is interpolated by a factor of two. 
     
     
       8. The method of  claim 1 , wherein the modulated subcarriers of the plurality of signals correspond to orthogonal frequency division multiplexed signals. 
     
     
       9. The method of  claim 1 , wherein shifting two or more of the plurality of increased sample rate signal in frequency by a multiple of the initial sample rate comprises shifting each signal by −R*(N−1)/2+(K−1)*R, where R is the initial sample rate, K is an index number of the signal, and N is the total number of signals in the plurality of signals. 
     
     
       10. The method of  claim 1 , wherein the method is a method of wireless communication. 
     
     
       11. The method of  claim 1 , wherein, if the plurality of signals constitute an even number of signals, all of the plurality of increased sample rate signals are shifted with respect to a center frequency. 
     
     
       12. The method of  claim 1 , wherein, if the plurality of signals constitute an odd number of signals, all but one of the plurality of increased sample rate signals are not shifted with respect to a center frequency. 
     
     
       13. A system comprising:
 an interpolator configured to receive a plurality of signals, each of the plurality of signals comprising a plurality of modulated subcarriers and having an initial sample rate, 
 wherein the interpolator is further configured to produce a plurality of interpolated signals by increasing a sample rate of each of the plurality of signals by a factor equal to a number of signals in the plurality of signals; 
 a frequency shifter configured to shift a frequency of two or more of the plurality of interpolated signals by a multiple of the initial sample rate to produce two or more frequency-shifted interpolated signals, wherein the frequency shifter is configured to shift based upon whether the plurality of signals constitute an even number of signals or an odd number of signals; and 
 an assimilator configured to assimilate two or more of the plurality of frequency-shifted interpolated signals and any of the plurality of interpolated signals not subject to shifting by the frequency shifter to produce an assimilated signal. 
 
     
     
       14. The system of  claim 13 , wherein the interpolator is configured to increase the sample rate by a factor of two. 
     
     
       15. The system of  claim 13 , wherein the received plurality of signals correspond to orthogonal frequency division multiplexed signals. 
     
     
       16. The system of  claim 13 , wherein the frequency shifter is configured to shift two or more of the plurality of interpolated signals by −R*(N−1)/2+(k−1)*R, where R is the initial sample rate, N is the total number of signals in the plurality of signals, and K is the signal's index number. 
     
     
       17. The system of  claim 13 , wherein the frequency shifter is configured to shift all of the plurality of interpolated signals with respect to a center frequency if the plurality of signals constitute an even number of signals. 
     
     
       18. The system of  claim 13 , wherein the frequency shifter is configured to shift all but one of the plurality of interpolated signals with respect to a center frequency if the plurality of signals constitute an odd number of signals. 
     
     
       19. A device comprising:
 a processor; and
 a memory having instructions stored thereon that, in response to being executed by a processor, the instructions cause the device to 
 obtain a plurality of signals, each of the plurality of signals comprising a plurality of modulated subcarriers and having an initial sample rate; 
 interpolate each of the plurality of signals by a factor equal to a number of signals in the plurality of signals to produce a plurality of interpolated signals; 
 shift two or more of the plurality of interpolated signals in frequency by a multiple of the initial sample rate to produce two or more frequency-shifted interpolated signals, wherein the means for shifting is configured to shift based upon whether the plurality of signals constitute an even number of signals or an odd number of signals; and 
 sum the two or more of frequency-shifted interpolated signals and any of the plurality of interpolated signals not subject to shifting to produce a summation signal. 
 
 
     
     
       20. The device of  claim 19 , wherein the instructions cause the device to shift each signal by −R*(N−1)/2+(K−1)*R, where R is the initial sample rate, N is the total number of signals in the plurality of signals, and K is the signal's index number. 
     
     
       21. The device of  claim 19 , wherein the instructions cause the device to shift all of the plurality of interpolated signals with respect to a center frequency if the plurality of signals constitute an even number of signals. 
     
     
       22. The device of  claim 19 , wherein the instructions cause the device to shift all but one of the plurality of interpolated signals with respect to a center frequency if the plurality of signals constitute an odd number of signals. 
     
     
       23. A transmitter comprising:
 a first input communicatively coupled to a processor, the first input configured to receive a first signal comprising a plurality of orthogonal frequency division multiplexed subcarriers, the first signal having a sample rate of approximately 20 MHz and a center frequency f c ; 
 the processor configured to interpolate the first signal to increase the sample rate of the first signal such that it has a sample rate of approximately 40 MHz, the processor further configured to shift the center frequency of the first signal to (f c  +10 MHz) by multiplying the first signal by e j2Π10t  for time t; 
 a second input communicatively coupled to the processor, the second input configured to receive a second signal comprising a plurality of orthogonal frequency division multiplexed subcarriers, the second signal having a sample rate of approximately 20 MHz and a center frequency f c ; 
 the processor further configured to interpolate the second signal to increase the sample rate of the second signal such that it has a sample rate of approximately 40 MHz, the processor further configured to shift the center frequency of the second signal to (f c − 10 MHz) by multiplying the second signal by e j2Π10t ; 
 the processor further configured to add the shifted first signal to the shifted second signal to produce a third signal with a sample rate of 40 MHz and a center frequency of f c ; and 
 an output communicatively coupled to the processor, the output configured to transmit the third signal.