Silicon dioxide cantilever support and method for silicon etched structures

Abstract

A semiconductor device includes a semiconductor layer ( 2 ) having therein a cavity ( 4 ). A dielectric layer ( 3 ) is formed on the semiconductor layer. A plurality of etchant openings ( 24 ) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO 2 pillar ( 25 ) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer ( 34 ) on the dielectric layer covers the etchant openings.

1. A method for making a semiconductor device, comprising:
 forming a deep trench in a semiconductor layer; 
 filling the deep trench with SiO2; 
 providing a dielectric layer on the semiconductor layer and the SiO2; 
 forming a plurality of etchant openings through the dielectric layer, the etchant openings being proximate to the SiO2; and 
 introducing etchant through the etchant openings to etch a cavity in the semiconductor layer and thereby expose the SiO2 as a SiO2 pillar extending from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity, to thereby increase robustness of the semiconductor device. 
 
     
     
       2. The method of  claim 1 , wherein the method further comprises providing a cap layer above the dielectric layer to cover the etchant openings. 
     
     
       3. The method of  claim 1 , wherein the method further comprises providing a first thermocouple junction in a portion of the dielectric layer extending over the cavity, and providing a second thermocouple junction in another portion of the dielectric layer disposed directly on the semiconductor layer, and coupling the first and second thermocouple junctions to form a thermopile. 
     
     
       4. The method of  claim 1 , wherein the method further comprises providing a passive component in a portion of the dielectric layer extending over the cavity to provide low parasitic capacitance between the passive component and the semiconductor layer. 
     
     
       5. The method of  claim 1 , wherein the step of forming the deep trench further comprises forming the deep trench in a silicon layer, and wherein the method further comprises providing roll-on epoxy a cap layer above the dielectric layer to cover the etchant openings.