Electrostatic discharge circuit

Abstract

An electrostatic discharge device has relatively superior characteristics for protecting a gate insulation layer of an input buffer transistor of a semiconductor device from static electricity while minimizing signal delay. The electrostatic discharge circuit includes a main electrostatic discharge section configured to discharge static electricity inputted to an input/output pad to at least one voltage line, an input impedance section configured to adjust an amount of current flowing from the input/output pad depending upon a frequency of an input signal of the input/output pad, an auxiliary electrostatic discharge section connected to the input impedance section and configured to discharge the static electricity inputted to the input/output pad to the at least one voltage line, and an input buffer connected between the auxiliary electrostatic discharge section and an internal circuit.

1. An electrostatic discharge circuit, comprising:
 a main electrostatic discharge section configured to discharge static electricity inputted to an input/output pad to at least one voltage line; 
 an input impedance section configured to adjust an amount of current flowing from the input/output pad depending upon a frequency of an input signal of the input/output pad; 
 an auxiliary electrostatic discharge section connected to the input impedance section and configured to discharge the static electricity inputted to the input/output pad to the at least one voltage line; and 
 an input buffer connected between the auxiliary electrostatic discharge section and an internal circuit, 
 wherein the input impedance section includes a resistor element and a capacitor element which are connected in parallel between the input/output pad and the auxiliary electrostatic discharge section and are each connected directly to each of the input/output pad and the auxiliary electrostatic discharge section. 
 
     
     
       2. The circuit of  claim 1 , wherein the main electrostatic discharge section includes a first main electrostatic discharge unit which is connected between the input/output pad and a power voltage line of the at least one voltage line and a second main electrostatic discharge unit which is connected between the input/output pad and a ground voltage line of the at least one voltage line. 
     
     
       3. The circuit of  claim 1 , wherein the auxiliary electrostatic discharge section includes a first auxiliary electrostatic discharge unit which is connected between the input impedance section and a power voltage line of the at least one voltage line and a second auxiliary electrostatic discharge unit which is connected between the input impedance section and a ground voltage line of the at least one voltage line. 
     
     
       4. The circuit of  claim 3 , wherein the first auxiliary electrostatic discharge unit includes a PMOS transistor having a drain which is connected to a gate of a PMOS transistor of the input buffer and a source which is connected to a source of the PMOS transistor of the input buffer. 
     
     
       5. The circuit of  claim 3 , wherein the second auxiliary electrostatic discharge unit comprises an NMOS transistor having a drain which is connected to a gate of an NMOS transistor of the input buffer and a source which is connected to a source of the NMOS transistor of the input buffer.