Driving device of plasma display panel and method

Abstract

A driving device of a plasma display panel for performing a reset period using a ramp pulse. The driving device changes the lowest potential of the ramp down pulse in response to temperature change in order to prevent or reduce low discharge or over-discharge due to the temperature change. The amount of wall charges in the pixels are maintained substantially constant over a temperature range to provide an optimal discharge condition, making it possible to prevent the discharge error and perform the low voltage address operation, in the address period.

1. A driving device of a plasma display panel (PDP) having a plurality of pixels located at crossing of a plurality of first and second electrodes and a plurality of third electrodes, the driving device comprising:
 a sustain pulse supply for supplying a sustain voltage to the first electrodes; 
 a ramp pulse supply for supplying a ramp up pulse having a voltage that increases from the sustain voltage at a constant slope, and a ramp down pulse having a voltage that decreases from the sustain voltage at a constant slope, to the first electrodes; and 
 a scan voltage supply for supplying a first scan voltage and a second scan voltage to the first electrodes, 
 wherein the ramp pulse supply comprises a first transistor coupled between a voltage source and a ramp up pulse outputting node and configured as constant current source; a second transistor configured as constant current source, a source of the second transistor coupled to a second scan voltage inputting terminal for inputting the second scan voltage; a resistive element coupled to a drain of the second transistor, the resistance value of the resistive element changing in response to temperature change; and a voltage dropping element coupled between the resistive element and a ramp down pulse outputting node. 
 
     
     
       2. The driving device of the PDP as claimed in  claim 1 , wherein the sustain pulse supply comprises:
 a capacitor coupled between a first node and a ground; 
 a third transistor and a first diode serially coupled between the first node and a second node; 
 a fourth transistor and a second diode serially coupled between the first and second nodes; 
 an inductor coupled between the second node and the ramp up pulse outputting node; 
 a fifth transistor coupled between a sustain voltage inputting terminal and the ramp up pulse outputting node; and 
 a sixth transistor coupled between the ramp up pulse outputting node and the ground. 
 
     
     
       3. The driving device of the PDP as claimed in  claim 1 , further comprising a third transistor coupled between the ramp down pulse outputting node and the ramp up pulse outputting node. 
     
     
       4. The driving device of the PDP as claimed in  claim 1 , further comprising a first capacitor coupled between a gate and a drain of the first transistor and a second capacitor coupled between a gate and the drain of the second transistor. 
     
     
       5. The driving device of the PDP as claimed in  claim 1 , further comprising:
 a first resistor coupled between the source of the first transistor and the ramp up pulse outputting node; and 
 a second resistor coupled between the source of the second transistor and the second scan voltage inputting terminal. 
 
     
     
       6. The driving device of the PDP as claimed in  claim 1 , wherein the resistive element comprises a thermistor having a resistance value that increases in response to temperature increase. 
     
     
       7. The driving device of the PDP as claimed in  claim 1 , wherein the resistive element comprises a thermistor having a resistance value that increases in response to temperature decrease. 
     
     
       8. The driving device of the PDP as claimed in  claim 1 , wherein the lowest potential of the ramp down pulse is determined according to the resistance value of the resistive element. 
     
     
       9. The driving device of the PDP as claimed in  claim 8 , wherein the lowest potential of the ramp down pulse increases when the resistance value of the resistive element increases. 
     
     
       10. The driving device of the PDP as claimed in  claim 8 , wherein the lowest potential of the ramp down pulse decreases when the resistance value of the resistive element decreases. 
     
     
       11. The driving device of the PDP as claimed in  claim 1 , wherein the voltage dropping element is a Zener diode. 
     
     
       12. The driving device of the PDP as claimed in  claim 1 , wherein the scan voltage supply comprises:
 a diode coupled between a first scan voltage inputting terminal for inputting the first scan voltage and an output node; 
 a capacitor coupled between the output node and the ramp down pulse outputting node; and 
 a third transistor coupled between the ramp down pulse outputting node and the second scan voltage inputting terminal. 
 
     
     
       13. The driving device of the PDP as claimed in  claim 1 , further comprising an output unit for transferring the sustain voltage, the ramp up pulse, the ramp down pulse, and the first scan voltage and the second scan voltage to the first electrodes. 
     
     
       14. The driving device of the PDP as claimed in  claim 13 , wherein the output unit comprises:
 a third transistor coupled between the first electrodes and the output node of the scan voltage supply; and 
 a fourth transistor coupled between the first electrodes and the ramp down pulse outputting node.