Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof

Abstract

A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method applied to these library cells includes the steps of rotating the second library cell to cause the metal track direction of the odd metal layers of the second library cell to be parallel to that of the odd metal layers of the first library cell, and placing the first library cell and the second library cell in an identical integrated circuit design.

1. An integrated circuit design method applied to a plurality of library cells having a first library cell and a second library cell, where both the first library cell and the second library cell respectively have a plurality of metal layers, and a metal track direction of odd metal layers of the first library cell is perpendicular to that of odd metal layers of the second library cell, the integrated circuit design method comprising:
 rotating the second library cell to make the metal track direction of odd metal layers of the rotated second library cell be parallel to that of the odd metal layers of the first library cell; and 
 using a computer to place the first library cell and the rotated second library cell in an identical integrated circuit design. 
 
     
     
       2. The integrated circuit design method of  claim 1 , wherein the first library cell is placed in a first block within the integrated circuit design and the second library cell is placed in a second block within the integrated circuit design, and the integrated circuit design method further comprises:
 planning power plans of the first block and the second block according to an identical metal track direction. 
 
     
     
       3. The integrated circuit design method of  claim 2 , further comprising:
 directly connecting a power rail of a designated metal layer within the rotated second library cell to the power plan of the first block through vias. 
 
     
     
       4. The integrated circuit design method of  claim 1 , wherein the first library cell is a normal cell and the second library cell is an ultra high speed cell. 
     
     
       5. The integrated circuit design method of  claim 1 , wherein the first library cell is an ultra high speed cell and the second library cell is a normal cell. 
     
     
       6. The integrated circuit design method of  claim 1 , both the first library cell and the second library cell respectively comprise six metal layers. 
     
     
       7. An integrated circuit design system applied to a plurality of library cells having a first library cell and a second library cell, the first library cell and the second library cell respectively having a plurality of metal layers, and a metal track direction of odd metal layers of the first library cell being perpendicular to that of odd metal layers of the second library cell, the integrated circuit design system comprising:
 a rotating module, for rotating the second library cell to make the metal track direction of odd metal layers of the rotated second library cell be parallel to that of the odd metal layers of the first library cell; and 
 an element placing module, for placing the first library cell and the rotated second library cell in an identical integrated circuit design. 
 
     
     
       8. The integrated circuit design system of  claim 7 , wherein the element placing module places the first library cell in a first block within the integrated circuit design and places the second library cell in a second block within the integrated circuit design, and the integrated circuit design system further comprises:
 a power planning module, for planning power plans of the first block and the second block according to an identical metal track direction. 
 
     
     
       9. The integrated circuit design system of  claim 8 , further comprising:
 a metal layer connecting module, for directly connecting a power rail of a designated metal layer within the rotated second library cell to the power plan of the first block through vias. 
 
     
     
       10. The integrated circuit design system of  claim 7 , wherein the first library cell is a normal cell and the second library cell is an ultra high speed cell. 
     
     
       11. The integrated circuit design system of  claim 7 , wherein the first library cell is an ultra high speed cell and the second library cell is a normal cell. 
     
     
       12. The integrated circuit design system of  claim 7 , wherein both the first library cell and the second library cell respectively comprise six metal layers.