Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block.

1. A nonvolatile semiconductor memory device, comprising:
 a memory cell array configured to have a plurality of blocks arranged thereon, each of said blocks being configured by an assembly of NAND cell units, each of said NAND cell units including a plurality of nonvolatile memory cells connected in series and having a first select gate transistor and a second select gate transistor disposed at respective ends thereof; 
 word lines configured to commonly connect control gates of said memory cells aligned in a first direction; and 
 a first select gate line and a second select gate line configured to commonly connect gates of said first select gate transistors and said second select gate transistors aligned in said first direction, respectively, 
 a data erase operation in said nonvolatile semiconductor memory device being executed by first applying a pre-charge voltage to said word lines, then setting to a floating state said word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to said word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where said memory cell array is formed, thereby altering a threshold voltage of said memory cells in said selected block. 
 
     
     
       2. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said pre-charge voltage is applied to all of said word lines in said memory cell array. 
 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said pre-charge voltage is applied only to said word lines in said non-selected block. 
 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said non-selected block is an initial setting region where initial setting data is stored. 
 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 4 ,
 wherein said data erase operation is configured to erase all of data stored in a region except for said initial setting region. 
 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said memory cells are MONOS memory cells. 
 
     
     
       7. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said memory cells are floating gate memory cells. 
 
     
     
       8. The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein said data erase operation is executed for a certain period of time, and 
 wherein a voltage value of said pre-charge voltage is set so that, when said certain period of time has elapsed and a voltage of said word lines in said non-selected block has fallen, said word lines in said non-selected block maintain a voltage value causing no erase operation in said memory cells. 
 
     
     
       9. A nonvolatile semiconductor memory device, comprising:
 a memory cell array configured to have a plurality of blocks arranged thereon, each of said blocks being configured by an assembly of NAND cell units, each of said NAND cell units including a plurality of nonvolatile memory cells connected in series and having a first select gate transistor and a second select gate transistor disposed at respective ends thereof; 
 word lines configured to commonly connect control gates of said memory cells aligned in a first direction, said word lines having a pre-charge voltage applied thereto; and 
 a first select gate line and a second select gate line configured to commonly connect gates of said first select gate transistors and said second select gate transistors aligned in said first direction, respectively, 
 a data erase operation in said nonvolatile semiconductor memory device being executed by setting to a floating state said word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to said word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where said memory cell array is formed, thereby altering a threshold voltage of said memory cells in said selected block. 
 
     
     
       10. The nonvolatile semiconductor memory device according to  claim 9 ,
 wherein said non-selected block is an initial setting region where initial setting data is stored. 
 
     
     
       11. The nonvolatile semiconductor memory device according to  claim 10 ,
 wherein said data erase operation is configured to erase all of data stored in a region except for said initial setting region. 
 
     
     
       12. The nonvolatile semiconductor memory device according to  claim 9 ,
 wherein said memory cells are MONOS memory cells. 
 
     
     
       13. The nonvolatile semiconductor memory device according to  claim 9 ,
 wherein said memory cells are floating gate memory cells. 
 
     
     
       14. The nonvolatile semiconductor memory device according to  claim 9 ,
 wherein said data erase operation is executed for a certain period of time, and 
 wherein a voltage value of said pre-charge voltage is set so that, when said certain period of time has elapsed and a voltage of said word lines in said non-selected block has fallen, said word lines in said non-selected block maintain a voltage value causing no erase operation in said memory cells. 
 
     
     
       15. A nonvolatile semiconductor memory device, comprising:
 a memory cell array configured to have a plurality of blocks arranged thereon, each of said blocks being configured by an assembly of NAND cell units, each of said NAND cell units including a plurality of nonvolatile memory cells connected in series and having a first select gate transistor and a second select gate transistor disposed at respective ends thereof; 
 word lines configured to commonly connect control gates of said memory cells aligned in a first direction; and 
 a first select gate line and a second select gate line configured to commonly connect gates of said first select gate transistors and said second select gate transistors aligned in said first direction, respectively, 
 a pre-charge voltage being previously applied to said word lines in a non-selected block where erasure of data is not to be executed, and 
 a data erase operation in said nonvolatile semiconductor memory device being executed by setting to a floating state said word lines in said non-selected block, applying a certain voltage to said word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where said memory cell array is formed, thereby altering a threshold voltage of said memory cells in said selected block. 
 
     
     
       16. The nonvolatile semiconductor memory device according to  claim 15 ,
 wherein said non-selected block is an initial setting region where initial setting data is stored. 
 
     
     
       17. The nonvolatile semiconductor memory device according to  claim 16 ,
 wherein said data erase operation is configured to erase all of data stored in a region except for said initial setting region. 
 
     
     
       18. The nonvolatile semiconductor memory device according to  claim 15 ,
 wherein said memory cells are MONOS memory cells. 
 
     
     
       19. The nonvolatile semiconductor memory device according to  claim 15 ,
 wherein said memory cells are floating gate memory cells. 
 
     
     
       20. The nonvolatile semiconductor memory device according to  claim 15 ,
 wherein said data erase operation is executed for a certain period of time, and 
 wherein a voltage value of said pre-charge voltage is set so that, when said certain period of time has elapsed and a voltage of said word lines in said non-selected block has fallen, said word lines in said non-selected block maintain a voltage value causing no erase operation in said memory cells.