Wide range interpolative voltage controlled oscillator

Abstract

Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

1. A voltage controlled oscillator (VCO) comprising:
 a ring of serially connected inverters; 
 a plurality of bypass circuits coupled to the ring of serially connected inverters,
 wherein the bypass circuits are configured to be selectively enabled, 
 wherein each bypass circuit is configured to bypass one or more of the serially connected inverters when the bypass circuit is enabled; and 
 
 a plurality of variable delay units, wherein each variable delay unit is configured to delay, by a variable amount, signal transitions at an input of a corresponding one of the serially connected inverters, 
 wherein each variable delay unit is coupled between a successive pair of the serially connected inverters, 
 wherein each variable delay unit is configured to be selectively enabled, and 
 wherein each variable delay unit is configured to provide a variable conductance between the successive pair of the serially connected inverters. 
 
     
     
       2. The VCO of  claim 1 , wherein each variable delay unit includes a first transistor and a delay component, wherein the first transistor and the delay component are coupled in parallel between an input of the variable delay unit and an output of the variable delay unit. 
     
     
       3. The VCO of  claim 2 , wherein the delay component comprises a second transistor, wherein a control voltage VC is applied to a gate of the first transistor and wherein a bias voltage VB is applied to a gate of the second transistor. 
     
     
       4. The VCO of  claim 3 , wherein the first transistor comprises a low-impedance transistor and the second transistor comprises a high-impedance transistor. 
     
     
       5. The VCO of  claim 3 , wherein the variable delay unit further comprises a bias voltage generator configured to produce a selectable bias voltage. 
     
     
       6. The VCO of  claim 5 , wherein the bias voltage generator comprises a multiplexer, wherein a plurality of different voltages are input to the multiplexer, and wherein a bias control signal is applied to a control input of the multiplexer to select one of the plurality of input voltages and to output the selected input voltage as the bias voltage. 
     
     
       7. The VCO of  claim 2 , wherein the delay component comprises a resistor. 
     
     
       8. A voltage controlled oscillator (VCO) comprising:
 a ring of serially connected inverters; 
 a plurality of bypass circuits coupled to the ring of serially connected inverters,
 wherein the bypass circuits are configured to be selectively enabled, 
 wherein each bypass circuit is configured to bypass one or more of the serially connected inverters when the bypass circuit is enabled; and 
 
 a plurality of variable delay units, wherein each variable delay unit is configured to delay, by a variable amount, signal transitions at an input of a corresponding one of the serially connected inverters, 
 wherein each variable delay unit is coupled to the ring of serially connected inverters in parallel with a corresponding one of the bypass circuits, 
 wherein the variable delay unit has a gain which is opposite a gain of the corresponding bypass circuit. 
 
     
     
       9. The VCO of  claim 8 , wherein the variable delay unit comprises a buffer. 
     
     
       10. The VCO of  claim 9 , wherein the bypass circuit comprises an inverter and wherein the gain of the buffer is opposite the gain of the inverter. 
     
     
       11. The VCO of  claim 10 , wherein the bypass circuit further comprises a first transistor coupled in series with the inverter, wherein the variable delay unit further comprises a second transistor coupled in series with the buffer, and wherein the first and second transistors are controlled so that the conductance of the first transistor is increased when the conductance of the second transistor is decreased, and decreased when the conductance of the second transistor is increased. 
     
     
       12. The VCO of  claim 11 , wherein one of the first and second transistors is a PMOS transistor and the other of the first and second transistors is an NMOS transistor, and wherein the control voltage VC is applied to the gates of both the first and second transistors. 
     
     
       13. A voltage controlled oscillator (VCO) comprising:
 a ring of serially connected inverters; 
 a plurality of bypass circuits coupled to the ring of serially connected inverters,
 wherein the bypass circuits are configured to be selectively enabled, 
 wherein each bypass circuit is configured to bypass one or more of the serially connected inverters when the bypass circuit is enabled; and 
 
 a plurality of variable delay units, wherein each variable delay unit is configured to delay, by a variable amount, signal transitions at an input of a corresponding one of the serially connected inverters, 
 wherein each variable delay unit is coupled in parallel to one of the serially connected inverters with an input of the variable delay unit coupled to an input of the inverter and an output of the variable delay unit coupled to an output of the inverter, 
 wherein each variable delay unit is configured to be selectively enabled, 
 wherein each variable delay unit is configured to delay a signal input to the variable delay unit by an amount greater than an amount by which the signal is delayed by the inverter. 
 
     
     
       14. The VCO of  claim 13 , wherein each variable delay unit comprises a plurality of inverters which are serially connected between the input and output of the variable delay unit. 
     
     
       15. The VCO of  claim 14 , wherein each variable delay unit further comprises a delay unit transistor coupled in series with the plurality of inverters between the input and output of the variable delay unit. 
     
     
       16. The VCO of  claim 15 , wherein each bypass circuit comprises an inverter in series with a bypass transistor and wherein the delay unit and bypass transistors are controlled so that the conductance of the delay unit transistor is increased when the conductance of the bypass transistor is decreased, and decreased when the conductance of the bypass transistor is increased. 
     
     
       17. The VCO of  claim 13 , wherein each variable delay unit comprises at least one inverter and one or more delay components which are serially connected between the input and output of the variable delay unit.