Memory cell

Abstract

Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.

1. A method for reading a programmable memory cell, comprising:
 supplying a bias current to the programmable memory cell to produce a bias voltage; 
 limiting the bias voltage across the programmable memory cell to approximately a threshold voltage (Vt) of a bias transistor; 
 using the bias current supplied to the programmable memory cell as negative feedback to the bias transistor to maintain a junction voltage of the bias transistor; and 
 wherein the junction voltage of the bias transistor is within a read voltage region of the programmable memory cell. 
 
     
     
       2. The method of  claim 1 , wherein the bias current is supplied to a programmable volume of the programmable memory cell, and wherein the programmable volume has more than one resistance state. 
     
     
       3. The method of  claim 2 , wherein the read voltage region includes voltages less than those associated with re-programming the resistance state of the programmable volume. 
     
     
       4. The method of  claim 1 , wherein the bias voltage is limited the threshold voltage (Vt) of the bias transistor plus or minus 10 mV. 
     
     
       5. The method of  claim 4 , wherein the bias transistor is a NMOS field effect transistor. 
     
     
       6. The method of  claim 1 , wherein using the bias current supplied to the programmable memory cell as negative feedback to the bias transistor includes applying the bias voltage to the gate of the bias transistor, bias voltage of at least Vt causing the bias transistor to turn on, the bias transistor being configured to reduce the bias current when turned-on so as to decrease the bias current and bias voltage. 
     
     
       7. The method of  claim 6 , wherein applying the bias voltage to the gate of the bias transistor includes applying the bias voltage through a select transistor to the gate of the bias transistor. 
     
     
       8. The method of  claim 7 , wherein the method includes passing the bias current through the select transistor. 
     
     
       9. The method of  claim 1 , wherein using the bias current supplied to the programmable memory cell as negative feedback to the bias transistor includes applying the bias voltage to the gate of the bias transistor, bias voltage of less than Vt causing the bias transistor to turn off, the bias transistor being configured to increase the bias current when turned off so as to increase the bias current and bias voltage. 
     
     
       10. The method of  claim 1 , wherein the method includes:
 applying a positive voltage to a gate of a transistor through which the bias current flows when the bias transistor is turned off; and 
 applying a reference voltage to the gate of the transistor through which the bias current flows when the bias transistor is turned on. 
 
     
     
       11. The method of  claim 10 , wherein the transistor through which the bias current flows is a NMOS field effect transistor. 
     
     
       12. The method of  claim 1 , wherein the method includes:
 turning on a transistor through which the bias current flows when the bias transistor is turned off; and 
 turning off a transistor through which the bias current flows when the bias transistor is turned on. 
 
     
     
       13. The method of  claim 1 , wherein the method includes maintaining the bias voltage slightly above or below the Vt of the bias transistor based on the resistance of the programmable memory cell. 
     
     
       14. A method for reading a programmable memory cell, comprising:
 supplying a bias current to the programmable memory cell to produce a bias voltage; 
 applying the bias voltage across a gate-source of a bias transistor; 
 pulling a gate voltage of a transistor through which the bias current flows to a ground potential as the bias transistor turns on thereby decreasing the bias current and the bias voltage; and 
 pulling the gate voltage of the transistor through which the bias current flows to a source potential as the bias transistor turns off thereby increasing the bias current and the bias voltage. 
 
     
     
       15. The method of  claim 14 , wherein the bias voltage is limited the threshold voltage (Vt) of the bias transistor plus or minus 10 mV, the Vt of the bias transistor plus or minus  10  mV being within the read voltage range of the programmable memory cell. 
     
     
       16. The method of  claim 14 , wherein the bias transistor and the transistor through which the bias current flows are each a NMOS field effect transistor. 
     
     
       17. A method for reading a programmable memory cell, comprising:
 supplying a bias current to the programmable memory cell to produce a bias voltage; 
 decreasing the bias current and the bias voltage in response to the bias voltage being at least a threshold voltage (Vt) of a bias transistor; and 
 increasing the bias current and the bias voltage in response to the bias voltage being less than the Vt of the bias transistor. 
 
     
     
       18. The method of  claim 17 , wherein the method includes applying the bias voltage to a gate of the bias transistor; and wherein the bias current does not pass through the bias transistor. 
     
     
       19. The method of  claim 17 , wherein decreasing the bias current includes changing a channel resistance of a transistor through which the bias current flows based on the state of the bias transistor.