Semiconductor memory device capable of increasing writing speed

Abstract

A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

1. A semiconductor memory device comprising:
 a memory cell array including a plurality of blocks including a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines; 
 a plurality of selection transistors which select the word lines; and 
 a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, and read and erase operations of data with respect to the memory cells, 
 wherein the plurality of selection transistors are formed on a well, and in read operation a first negative voltage is supplied to the well, a first group of the plurality of selection transistors connected to a non-selected of the plurality of blocks block is turned off, a second group of the plurality of selection transistors connected to a selected of the plurality of blocks block is turned on, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line. 
 
     
     
       2. The device according to  claim 1 , wherein at least one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell. 
     
     
       3. The device according to  claim 1 , wherein the control circuit includes a negative voltage generator circuit which generates the first negative voltage. 
     
     
       4. The device according to  claim 1 , wherein the plurality of selection transistors are included in a row decoder selecting the word line. 
     
     
       5. A semiconductor memory device comprising:
 a memory cell array including a plurality of blocks including a plurality of memory cells which are arranged in a matrix form and connected in series, the plurality of memory cells being connected with word lines and bit lines and the plurality of memory cells serving as a plurality of blocks; 
 a plurality of selection transistors which select the word lines; and 
 a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, and read and erase operations of data with respect to the memory cells, 
 wherein the plurality of selection transistors are formed on a well, and in the write operation a first negative voltage is supplied to the well, a first group of the plurality of selection transistors connected to a non-selected of the plurality of blocks block is turned off, a second group of the plurality of selection transistors connected to a selected of the plurality of blocks block is turned on, a first voltage (the first voltage≧the first negative voltage) is supplied to a predetermined non-selected word line. 
 
     
     
       6. The device according to  claim 5 , wherein one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell. 
     
     
       7. The device according to  claim 5 , wherein the first negative voltage is supplied to a gate electrode of a memory cell which is positioned on at least a source line side apart from a writing target memory cell. 
     
     
       8. The device according to  claim 5 , wherein the control circuit includes a negative voltage generator circuit which generates the first negative voltage. 
     
     
       9. The device according to  claim 5 , wherein the plurality of selection transistors are included in a row decoder selecting the word line. 
     
     
       10. A semiconductor memory device comprising:
 a memory cell array including a plurality of blocks including a plurality of memory cells arranged in a matrix form, the plurality of memory cells being connected with word lines and bit lines; 
 a plurality of selection transistors which select the word lines; and 
 a control circuit which controls potentials of the word lines and the bit lines in accordance with input data, the control circuit controlling write, and read and erase operations of data with respect to the memory cells, 
 wherein the plurality of selection transistors are formed on a well, and in an erase verify read operation a first negative voltage is supplied to the well, a first group of the plurality of selection transistors connected to a non-selected of the plurality of blocks block is turned off, a second group of the plurality of selection transistors connected to a selected of the plurality of blocks block is turned on, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line. 
 
     
     
       11. The device according to  claim 10 , wherein at least one of a plurality of negative threshold voltages and a plurality of positive threshold voltages is set with respect to the memory cell. 
     
     
       12. The device according to  claim 10 , wherein the control circuit includes a negative voltage generator circuit which generates the first negative voltage. 
     
     
       13. The device according to  claim 10 , wherein the plurality of selection transistors are included in a row decoder selecting the word line.