Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device includes a semiconductor substrate that includes a trench, a charge storage layer that is formed inside of the trench, a first gate that is formed above a side surface and a bottom surface of the trench, a second gate that is formed beside the first gate, and that is formed above the charge storage layer, a first diffusion region that is formed on the semiconductor substrate inside of the trench, and a second diffusion region that is formed on the semiconductor substrate outside of the trench.

1. A nonvolatile semiconductor memory device, comprising:
 a semiconductor substrate that includes a trench; 
 a charge storage layer that is formed inside of the trench; 
 a first gate that is formed above a side surface and a bottom surface of the trench; 
 a second gate that is formed beside the first gate, and that is formed above the charge storage layer; 
 a first diffusion region that is formed on the semiconductor substrate inside of the trench; and 
 a second diffusion region that is formed on the semiconductor substrate outside of the trench, 
 wherein, in a cross sectional view, an entirety of a region of a top surface of the first gate is silicided. 
 
     
     
       2. The nonvolatile semiconductor memory device according to  claim 1 , wherein the first gate is adjacent to the second gate. 
     
     
       3. The nonvolatile semiconductor memory device according to  claim 1 , wherein the semiconductor substrate comprises:
 a channel region along the side surface and the bottom surface of the trench. 
 
     
     
       4. The nonvolatile semiconductor memory device according to  claim 3 , wherein the channel region comprises:
 a first channel region corresponding to a lower portion of the second gate; 
 a second channel region corresponding to a lower portion of the first gate; and 
 a third channel region corresponding to a side portion of the first gate. 
 
     
     
       5. The nonvolatile semiconductor memory device according to  claim 1 , wherein the first diffusion region is located at a position deeper than the second diffusion region. 
     
     
       6. The nonvolatile semiconductor memory device according to  claim 1 , wherein the first diffusion region is formed at a position corresponding to an area beside the second gate. 
     
     
       7. The nonvolatile semiconductor memory device according to  claim 1 , wherein the second gate is formed as a side wall of the first gate through an insulating layer, and includes a surface having a curved shape. 
     
     
       8. The nonvolatile semiconductor memory device according to  claim 1 , further comprising:
 an insulating layer that is formed above the second gate; 
 a silicide layer that is formed above the insulating layer; and 
 an interlayer insulating film that is formed above the silicide layer. 
 
     
     
       9. The nonvolatile semiconductor memory device according to  claim 1 , wherein the region of the top surface of the first gate comprises a silicide control gate that abuts the top surface of the first gate. 
     
     
       10. The nonvolatile semiconductor memory device according to  claim 1 , wherein the region of the top surface of the first gate comprises a silicide control gate that abuts the charge storage layer. 
     
     
       11. The nonvolatile semiconductor memory device according to  claim 1 , wherein the second diffusion region abuts the charge storage layer. 
     
     
       12. The nonvolatile semiconductor memory device according to  claim 1 , further comprising:
 an insulating layer disposed on an upper surface of the second gate, 
 wherein the region of the top surface of the first gate comprises a silicide control gate that abuts the insulating layer. 
 
     
     
       13. The nonvolatile semiconductor memory device according to  claim 1 , wherein an entirety of the top surface of the first gate is silicided.