Analog/digital converter and semiconductor integrated circuit device

Abstract

In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

1. A semiconductor integrated circuit device in which an A/D converter comprising M unitary A/D conversion units different in phase and equal in sampling rate, where M is an integer equal to or larger than 2, the A/D conversion units being connected in parallel to each other, the A/D converter having a sampling rate M times as high as that of the unitary A/D conversion unit, is formed on a single semiconductor substrate together with a clock source, wherein
 in the A/D converter, 
 a reference A/D conversion unit having a lower sampling rate and a higher resolution than the unitary A/D conversion units is connected in parallel to the M unitary A/D conversion units, 
 when the sampling rate of the A/D converter is N times as high as the sampling rate of the reference A/D conversion unit, where N is an integer equal to or larger than 2, M and N are relatively prime to each other, and 
 the A/D converter has a function of performing calibration for each of the M unitary A/D conversion units based on an output of the reference A/D conversion unit, 
 each of the unitary A/D conversion units and the reference A/D conversion unit are arranged so that a space where none of each of the unitary A/D conversion units and the reference A/D conversion unit are arranged is minimized, and 
 there is a combination of the unitary A/D conversion units and the reference A/D conversion unit whose distances from the clock source are different from each other. 
 
     
     
       2. The semiconductor integrated circuit device according to  claim 1 , wherein
 the calibration is post-calibration to be performed in a digital region for each output of the M unitary A/D conversion units. 
 
     
     
       3. The semiconductor integrated circuit device according to  claim 2 , wherein
 the post-calibration is executed in a background during a normal operation of the A/D converter. 
 
     
     
       4. The semiconductor integrated circuit device according to  claim 1 , wherein
 a sampling timing of the unitary A/D conversion unit is generated by an operation clock input to each of the M unitary A/D conversion units, and 
 the sampling rate corresponds to an operation clock frequency, which is a frequency of the operation clock. 
 
     
     
       5. An A/D converter comprising:
 M unitary A/D conversion units different in phase and equal in sampling rate, where M is an integer equal to or larger than 2, the A/D conversion units being connected in parallel; 
 a reference A/D conversion unit connected in parallel to the M unitary A/D conversion units and having an operation clock frequency set to 1/N of an overall sampling rate of the A/D converter; and 
 M calibration units each performing calibration at an output of a corresponding unitary A/D conversion unit, and each having a sampling-timing calibration unit adapted to correct a sampling timing of the corresponding unitary A/D conversion unit so as to be equal to a sampling timing of the reference A/D conversion unit, 
 wherein each of the sampling-timing calibration units comprises: 
 a subtracting unit adapted to calculate a conversion error signal which is a difference between an output of the calibration unit and an output of the reference A/D conversion unit; 
 a time differentiation deriving portion that derives a time differentiation of an input signal to the sampling-timing calibration unit; 
 a multiplier adapted to multiply the conversion error signal and the time differentiation; and 
 an accumulator integrating an output of the multiplier, 
 wherein M and N are relatively prime to each other, and 
 wherein each of the sampling-timing calibration units performs calibration by using an output of the accumulator. 
 
     
     
       6. The A/D converter according to  claim 5 , wherein
 an LMS (Least Mean Square) algorithm is applied as an algorithm for the calibration. 
 
     
     
       7. The A/D converter according to  claim 5 , wherein the time differentiation deriving portion includes a difference unit. 
     
     
       8. The A/D converter according to  claim 5 , wherein
 the operation clock frequency of the reference A/D conversion unit is set to be smaller than an operation clock frequency of each of the unitary A/D conversion units. 
 
     
     
       9. The A/D converter according to  claim 5 , wherein
 the time differentiation deriving portion includes a first-order time differentiator. 
 
     
     
       10. The A/D converter according to  claim 9 , wherein
 an FIR filter having fixed tap coefficients obtained from a sampling theorem and a window function is used as the first-order time differentiator. 
 
     
     
       11. The A/D converter according to  claim 5 , wherein
 the time differentiation deriving portion further includes a second-order time differentiator. 
 
     
     
       12. The A/D converter according to  claim 11 , wherein
 an FIR filter having fixed tap coefficients obtained from a sampling theorem and a window function is used as the second order time differentiator. 
 
     
     
       13. The A/D converter according to  claim 5 , wherein
 each of the calibration units includes plural calibration stages that are cascade-connected. 
 
     
     
       14. The A/D converter according to  claim 13 , wherein the plurality of calibration stages include a calibration stage to correct sampling timing and at least one calibration stage to perform calibration of a parameter other than sampling timing. 
     
     
       15. The A/D converter according to  claim 14 , wherein said parameter is selected from the group consisting of conversion gain, DC offset voltage, non-linearity and frequency characteristics. 
     
     
       16. The A/D converter according to  claim 13 , wherein the plurality of calibration stages include a calibration stage to correct sampling timing and a plurality of stages to correct selected parameters selected from the group consisting of conversion gain, DC offset voltage, non-linearity and frequency characteristics. 
     
     
       17. The A/D converter according to  claim 5 , wherein
 at least one of the operation clock frequency of the reference A/D conversion unit and an operation clock frequency of each of the unitary A/D conversion units is generated by using an odd number/2 frequency divider. 
 
     
     
       18. The A/D converter according to  claim 5 , wherein
 at least one of the operation clock frequency of the reference A/D conversion unit and an operation clock frequency of each of the unitary A/D conversion units is generated by using a DLL (Delay Locked Loop) circuit and an edge combiner circuit.