Dynamic signal calibration for a high speed memory controller

Abstract

Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the delay circuit. The new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span. The method can include dynamically adjusting a delay applied to a signal by a delay circuit according to the new tap setting. The delay circuit generates a delayed signal that is provided to the memory controller.

What is claimed is: 
     
       1. Within an integrated circuit comprising a memory controller, a method comprising:
 responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting specifying a delay applied to a signal by a delay circuit, wherein the new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span; and 
 dynamically adjusting the delay applied to the signal by the delay circuit according to the new tap setting, wherein the delay circuit generates a delayed signal that is provided to the memory controller. 
 
     
     
       2. The method of  claim 1 , wherein calculating a new tap setting further comprises:
 determining the new tap setting according to a ratio of the new maximum value to an old maximum value. 
 
     
     
       3. The method of  claim 1 , wherein calculating a new tap setting further comprises:
 determining the new tap setting according to a product of a ratio of the new maximum value to an old maximum value and the old tap setting. 
 
     
     
       4. The method of  claim 3 , wherein calculating a new tap setting is performed using binary values, wherein determining the new tap setting further comprises:
 first, determining a first result for 2 N  divided by the old maximum value, wherein N is an even integer; 
 second, determining a second result by multiplying the first result by the new maximum value; 
 third, determining a third result by dividing the second result by 2 N/2 ; 
 fourth, determining a fourth result by multiplying the third result by the old tap setting; and 
 fifth, determining the new tap setting by dividing the fourth result by 2 N/2 . 
 
     
     
       5. The method of  claim 4 , wherein determining a first result for 2 N  divided by the old maximum value further comprises:
 determining the first result from a look-up table comprising results for 2 N  over a specified range of values for the old maximum value. 
 
     
     
       6. The method of  claim 5 , further comprising:
 determining the third result by shifting the second result N/2 bits to the right; and 
 determining the new tap setting by shifting the fourth result N/2 bits to the right. 
 
     
     
       7. The method of  claim 1 , further comprising completing the calculating of the new tap setting prior to completion of the refresh operation. 
     
     
       8. The method of  claim 1 , further comprising completing the dynamically adjusting of the delay according to the new tap setting prior to completion of the refresh operation. 
     
     
       9. A system disposed within an integrated circuit, the system comprising:
 a delay circuit configured to apply a delay to a signal generating a delayed signal provided to a memory controller; 
 a measurement circuit configured to calculate a new maximum value specifying a number of taps of the delay circuit that approximates a predetermined time span; and 
 a calibration controller coupled to the delay circuit and the measurement circuit, wherein the calibration controller is configured to calculate a new tap setting for the delay circuit according to the new maximum value and an old tap setting of the delay circuit responsive to determining that a memory controller is performing a refresh operation, 
 wherein the calibration controller dynamically adjusts the delay applied to the signal by the delay circuit according to the new tap setting. 
 
     
     
       10. The system of  claim 9 , wherein the calibration controller is further configured to calculate the new tap setting according to a ratio of the new maximum value to an old maximum value. 
     
     
       11. The system of  claim 9 , wherein the calibration controller is further configured to determine the new tap setting according to a product of a ratio of the new maximum value to an old maximum value and the old tap setting. 
     
     
       12. The system of  claim 11 , wherein the calibration controller is further configured to calculate a new tap setting using binary values by:
 first, determining a first result for 2 N  divided by the old maximum value, wherein N is an even integer; 
 second, determining a second result by multiplying the first result by the new maximum value; 
 third, determining a third result by dividing the second result by 2 N/2 ; 
 fourth, determining a fourth result by multiplying the third result by the old tap setting; and 
 fifth, determining the new tap setting by dividing the fourth result by 2 N/2 . 
 
     
     
       13. The system of  claim 12 , wherein the calibration controller further comprises a look-up table storing a plurality of first results corresponding to possible values of old maximum value from which the first result is determined. 
     
     
       14. The system of  claim 13 , wherein the calibration controller further comprises:
 at least one shifter determining the third result by shifting the second result N/2 bits to the right and determining the new tap setting by shifting the fourth result N/2 bits to the right. 
 
     
     
       15. The system of  claim 9 , wherein the calibration controller is further configured to complete the calculation of the new tap setting prior to completion of the refresh operation. 
     
     
       16. The system of  claim 15 , wherein the calibration controller is further configured to complete the dynamic adjustment of the delay according to the new tap setting prior to completion of the refresh operation. 
     
     
       17. A calibration controller disposed within an integrated circuit, the calibration controller comprising:
 first circuitry configured to calculate a new tap setting for a delay circuit according to a new maximum value and an old tap setting of the delay circuit responsive to determining that a memory controller is performing a refresh operation, wherein the new maximum value specifies a number of taps of the delay circuit that approximates a predetermined time span; and 
 second circuitry coupled to the first circuitry, wherein the second circuitry is configured to dynamically adjust the delay applied to the signal according to the new tap setting by outputting the new tap setting to the delay circuit, 
 wherein the first and second circuitry are operational to calculate the new tap setting and adjust the delay prior to completion of the refresh operation. 
 
     
     
       18. The calibration controller of  claim 17 , wherein the first circuitry is further configured to determine the new tap setting according to a ratio of the new maximum value to an old maximum value. 
     
     
       19. The calibration controller of  claim 17 , wherein the first circuitry is further configured to determine the new tap setting according to a product of a ratio of the new maximum value to an old maximum value and the old tap setting. 
     
     
       20. The calibration controller of  claim 19 , wherein the first circuitry further comprises:
 a look-up table configured to determine a first result for 2 N  divided by the old maximum value, wherein N is an even integer; 
 at least one multiplier configured to determine a second result by multiplying the first result by the new maximum value; and 
 at least one shifter configured to determine a third result by shifting the second result by N/2 bits to the right; 
 wherein the at least one multiplier is further configured to determine a fourth result by multiplying the third result by the old tap setting; and 
 wherein the at least one shifter is further configured to determine the new tap setting by shifting the fourth result by N/2 bits to the right.