Method for fabricating semiconductor device with damascene bit line

Abstract

A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.

What is claimed is: 
     
       1. A method for fabricating a semiconductor device, comprising:
 forming an interlayer dielectric layer over a substrate; 
 forming a dual storage node contact plug to be buried in the interlayer dielectric layer; 
 forming a first damascene pattern to isolate the dual storage node contact plug; 
 forming a protective layer pattern inside the first damascene pattern; 
 etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern; and 
 forming bit lines inside the first and second damascene patterns. 
 
     
     
       2. The method of  claim 1 , wherein the forming of the protective layer pattern comprises:
 forming a protective layer over the entire surface of the resultant substrate structure formed after the forming of the first damascene pattern so as to gap-fill the first damascene pattern; and 
 blanket-etching the protective layer. 
 
     
     
       3. The method of  claim 2 , wherein the protective layer comprises a carbon layer. 
     
     
       4. The method of  claim 3 , wherein the carbon layer comprises spin on carbon layer. 
     
     
       5. The method of  claim 4 , wherein, in the blank-etching of the protective layer, oxygen-based plasma is used. 
     
     
       6. The method of  claim 2 , wherein the protective layer comprises a photoresist layer. 
     
     
       7. The method of  claim 1 , further comprising forming a spacer on sidewalls of the first and second damascene patterns, before the forming of the bit lines. 
     
     
       8. The method of  claim 1 , wherein the dual storage node contact plug comprises a polysilicon layer and the interlayer dielectric layer comprises an oxide layer. 
     
     
       9. The method of  claim 1 , wherein, in the forming of the first damascene pattern and the second damascene pattern, a damascene mask which simultaneously opens the dual storage node contact plug and the interlayer dielectric layer in a line shape is used as an etch barrier. 
     
     
       10. The method of  claim 1 , wherein the forming of the protective layer pattern inside the first damascene pattern is performed before the etching of the interlayer dielectric layer to form the second damascene pattern. 
     
     
       11. The method of  claim 1 , further comprising forming of a spacer and etching the spacer inside the first and second damascene patterns before the forming of the bit lines, wherein the spacer remains at the bottom of the first damascene pattern after the spacer etching and does not remain at the bottom of the second damascene pattern after the spacer etching. 
     
     
       12. A method for fabricating a semiconductor device, comprising:
 forming a plurality of active regions in a substrate, the active regions being isolated by an isolation layer; 
 forming an interlayer dielectric layer over the substrate; 
 etching the interlayer dielectric layer to form a dual storage node contact hole which simultaneously opens adjacent ones of the active regions; 
 forming a dual storage node contact plug to be buried in the dual storage node contact hole; 
 forming a first damascene pattern to isolate the dual storage node contact plug into independent storage node contact plugs; 
 forming a protective layer pattern inside the first damascene pattern; 
 etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern; and 
 forming bit lines inside the first and second damascene patterns. 
 
     
     
       13. The method of  claim 12 , further comprising forming trenches by etching the active regions and the isolation layer and forming buried gates to partially fill the trenches before the forming of the interlayer dielectric layer. 
     
     
       14. The method of  claim 12 , further comprising forming a first landing plug and a second landing plug over the substrate before the forming of the interlayer dielectric layer, wherein the first landing plug is coupled to the bit line and the second landing plug is coupled to the storage node contact plug. 
     
     
       15. The method of  claim 12 , wherein the forming of the protective layer pattern comprises:
 forming a protective layer over the entire surface of the resultant substrate structure formed by the forming of the first damascene pattern so as to gap-fill the first damascene pattern; and 
 blanket-etching the protective layer. 
 
     
     
       16. The method of  claim 15 , wherein the protective layer comprises spin on carbon layer or a photoresist layer. 
     
     
       17. The method of  claim 15 , wherein, in the blank-etching of the protective layer, oxygen-based plasma is used. 
     
     
       18. The method of  claim 12 , further comprising forming a spacer on sidewalls of the first and second damascene patterns, before the forming of the bit lines. 
     
     
       19. The method of  claim 12 , wherein the dual storage node contact plug comprises a polysilicon layer and the interlayer dielectric layer comprises an oxide layer. 
     
     
       20. The method of  claim 12 , wherein, in the forming of the first damascene pattern and the second damascene pattern, a damascene mask which simultaneously opens the dual storage node contact plug and the interlayer dielectric layer in a line shape is used as an etch barrier.