Input buffer, test switches and switch control with serial I/O

Abstract

The peripheral circuitry ( 350, 360 , ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

What is claimed is: 
     
       1. A semiconductor body having at least one integrated circuit formed at a surface thereof, the at least one integrated circuit comprising:
 A. a core functional input; 
 B. an input terminal pad; 
 C. an input buffer having an input coupled to the input terminal pad and an output coupled with the core functional input; 
 D. a first test lead, a second test lead, and a third test lead; 
 E. a first test switch having a lead connected to the output of the input buffer, a lead connected to the first test lead, and a control input; 
 F. a second test switch having a lead connected to the input of the input buffer, a lead connected to the second test lead, and a control input; and 
 G. switch control circuitry having outputs connected to the control inputs of the first test switch and the second test switch, the switch control circuitry including a multiplexer having an output connected to the input of a capture-shift memory, the capture-shift memory having an output connected to the input of an update memory, the update memory having a control output connected to the control input of a switch, the multiplexer having an input connected to a serial test data input lead, and the output of the capture-shift memory being connected to a serial test data output lead. 
 
     
     
       2. The semiconductor body of  claim 1  including an electrostatic discharge protection circuit connected between the input terminal pad and the input of the input buffer. 
     
     
       3. The semiconductor body of  claim 1  including a bus holder circuit connected to the input of the input buffer. 
     
     
       4. The semiconductor body of  claim 1  including boundary scan circuitry coupled to the output of the input buffer.