Memory system protected from errors due to read disturbance and reading method thereof

Abstract

A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, and copying data from the first block of the flash memory to a second block of the flash memory when the counter exceeds a reference number of read-out cycles. The data from the first block includes data from the page.

What is claimed is: 
     
       1. A method of reading a flash memory, comprising:
 reading a first page in a first block of the flash memory; 
 incrementing a count of read-out cycles in connection with the reading of the first page; 
 comparing a reference value with the count of read-out cycles; 
 copying data from the first block to a second block of the flash memory in response to the comparing; and 
 storing the count of read-out cycles into the flash memory before powering down. 
 
     
     
       2. The method as set forth in  claim 1 , further comprising storing in a RAM the count of read-out cycles. 
     
     
       3. The method as set forth in  claim 2 , wherein the RAM is a DRAM or a SRAM. 
     
     
       4. The method as set forth in  claim 2 , further comprising copying table information stored as meta-data in the flash memory to the RAM. 
     
     
       5. The method as set forth in  claim 1 , wherein the copying comprises a copy-back programming operation for copying the data from the first block to the second block of the flash memory. 
     
     
       6. The method as set forth in  claim 1 , wherein the reference number is set by a user. 
     
     
       7. The method as set forth in  claim 1 , wherein the count of read-out cycles is a count of read-out cycles of the first page. 
     
     
       8. The method of  claim 1 , wherein the flash memory is a NAND flash memory. 
     
     
       9. The method of  claim 1 , wherein the flash memory is configured to store multi-bit data. 
     
     
       10. A method of operating a MP3 player comprising the method of  claim 1 . 
     
     
       11. A method of operating a Secure Digital card comprising the method of  claim 1 . 
     
     
       12. The method as set forth in  claim 1 , further comprising:
 controlling the flash memory with a memory controller; and 
 storing the counted number of read-out cycles in a storage unit. 
 
     
     
       13. The method as set forth in  claim 12 , further comprising copying table information stored as meta-data in the flash memory to the storage unit. 
     
     
       14. The method as set forth in  claim 12 , further comprising copying the counted number of read-out cycles from the flash memory into the storage unit in response to the memory system being powered on. 
     
     
       15. A method of reading a flash memory comprising:
 receiving a request by a host to access music data stored in the flash memory; 
 repeatedly reading a page of a first block of the flash memory in which the music data is stored; 
 analyzing a risk of read failure due to a read disturbance in the first block of the flash memory, wherein the step of analyzing comprises comparing a read-out cycle count to a reference number, the read-out cycle count being incremented in connection with the reading of the music data in the page of the first block, and the method further; 
 in response to the analyzing, causing the music data to be copied to a second block of the flash memory, and 
 storing the count of read-out cycles into the flash memory before powering down. 
 
     
     
       16. The method as set forth in  claim 15 , further comprising storing the read-out cycle count in a storage area of the flash memory. 
     
     
       17. The method as set forth in  claim 16 , wherein the storage area of the flash memory is located outside the first block and the second block. 
     
     
       18. The method of  claim 15 , wherein the flash memory is a NAND flash memory. 
     
     
       19. The method of  claim 15 , wherein the flash memory is configured to store multi-bit data. 
     
     
       20. The method of  claim 15 , wherein the step of analyzing comprises detecting a bit error caused by a soft programming. 
     
     
       21. A memory system comprising:
 a host interface; 
 a flash memory interface; 
 a flash memory comprising a plurality of blocks, each block comprising a plurality of pages; and 
 a memory controller configured to transfer data from the flash interface to the host interface on receiving a read request through the host interface, configured to read a page of a first block of the flash memory, configured to track a number of read-out cycles associated with the first block and configured to copy the data from the first block into a second block of the flash memory in response to the number of read-out cycles exceeding a reference number of read-out cycles and configured to cause the count of read-out cycles to be stored in the flash memory before powering down the memory system. 
 
     
     
       22. The memory system as set forth in  claim 21 , wherein the memory controller further comprises a host interface, a flash memory interface, a CPU, an ECC circuit and RAM, the memory controller operable to transfer data from the flash interface to the host interface on receiving a read request through the host interface, the ECC circuit of the memory controller operable to detect bit errors and to correct bit errors of the data. 
     
     
       23. The memory system as set forth in  claim 22 , wherein the flash memory controller further comprises a ROM configured to store boot codes. 
     
     
       24. The memory system as set forth in  claim 22 , wherein the CPU is configured to manage a FTL layer accessible from the RAM. 
     
     
       25. The memory system as set forth in  claim 22 , wherein the flash memory includes a meta-area to store meta-data. 
     
     
       26. The memory system as set forth in  claim 24 , wherein the controller is operable to copy the meta-data to the RAM of the controller. 
     
     
       27. The memory system as set forth in  claim 21 , wherein the flash memory is a NAND flash memory. 
     
     
       28. The memory system as set forth in  claim 21 , wherein the flash memory is configured to store multi-bit data. 
     
     
       29. The memory system as set forth in  claim 21 , wherein the memory controller comprises a count recorder to store a counted number of read-out cycles of the first block in the flash memory when one or more pages from the first block is read.