Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array

Abstract

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

1. A memory device, comprising:
 a plurality of cells, each cell comprising a memory element and a selection device; 
 a plurality of first address lines in a first plane; 
 a plurality of second address lines in a second plane extending across the plurality of first address lines, wherein at least some cells of the plurality of cells are connected at cross-points between the first address lines and the second address lines; 
 a plurality of third address lines in a third plane, wherein at least some cells of the plurality of cells are connected between cross-points of the second address lines and the third address lines; and 
 control circuitry configured to selectively apply a write voltage or a reference voltage substantially simultaneously to the plurality of first address lines and third address lines, and to selectively apply a write voltage, a reference voltage, or a voltage less than the write voltage, and greater than the reference voltage, substantially simultaneously to the plurality of second address lines. 
 
     
     
       2. The memory device of  claim 1 , wherein each cell of the plurality of cells comprises a bipolar memory element. 
     
     
       3. The memory device of  claim 2 , wherein each cell of the plurality of cells comprises a monopolar switching memory element comprising a phase-change memory element. 
     
     
       4. The memory device of  claim 1 , wherein each cell of the plurality of cells comprises a selection device comprising a material configured to retain at least substantially the same current-voltage characteristics. 
     
     
       5. The memory device of  claim 1 , wherein the control circuitry comprises:
 a first decode/enable circuit coupled to the plurality of first address lines and configured to provide the write voltage or the reference voltage substantially simultaneously to the plurality of first address lines; and 
 a second decode/enable circuit coupled to the plurality of second address lines and configured to provide the write voltage, the reference voltage or the voltage less than the write voltage and greater than the reference voltage substantially simultaneously to the plurality of second address lines. 
 
     
     
       6. A system, comprising:
 a memory access device; 
 a memory device coupled to the memory access device, the memory device comprising:
 a plurality of memory cells in a common plane, each memory cell comprising a memory element coupled to a selection device; 
 a plurality of first address lines in a first plane; 
 a plurality of second address lines in a second plane extending across the plurality of first address lines, wherein at least some cells of the plurality of cells are connected at cross-points between the first address lines and second address lines; 
 a plurality of third address lines in a third plane, wherein at least some cells of the plurality of cells are connected between cross-points of the second address lines and the third address lines; 
 a first decode/enable circuit configured to selectively apply a write voltage or a reference voltage to the first address lines and the third address lines; and 
 a second decode/enable circuit configured to selectively apply a write voltage, a reference voltage, or a voltage less than the write voltage, and greater than the reference voltage, to the plurality of second address lines such that at least some cells of the plurality of memory cells are accessed at least substantially simultaneously. 
 
 
     
     
       7. The system of  claim 6 , wherein the memory device comprises a Resistive Random Access Memory (RRAM). 
     
     
       8. The system of  claim 6 , wherein the memory device comprises a Phase-Change Random Access Memory (PCRAM).