Semiconductor integrated circuit device having a dummy metal wiring line

Abstract

There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

1. A semiconductor integrated circuit device comprising:
 a power supply line and a ground line each placed to extend in a first direction; and 
 first and second cells placed in a region interposed between the power supply line and the ground line to be adjacent to each other in the first direction, and each having a transistor and an intra-cell line each for implementing a circuit function, wherein 
 a dummy metal wiring line extending in a second direction orthogonal to the first direction is placed in a boundary portion between the first and second cells so as not to short-circuit the power supply line and the ground line, 
 a first metal wiring line in the first cell has a portion parallel with the dummy metal wiring line, the portion being connected with source or drain of a transistor and closest to the boundary portion between the first and second cells among the intra-cell line in the first cell, and 
 the first metal wiring line and the dummy metal wiring line are formed in a same wiring layer. 
 
     
     
       2. The semiconductor integrated circuit device of  claim 1 , wherein the dummy metal wiring line is in a floating state which is not connected to either of the power supply line and the ground line. 
     
     
       3. The semiconductor integrated circuit device of  claim 1 , wherein the dummy metal wiring line includes a first line formed to protrude from the power supply line, and a second line formed to protrude from the ground line, and unconnected to the first line. 
     
     
       4. The semiconductor integrated circuit device of  claim 1 , wherein the dummy metal wiring line is formed to protrude from the power supply line, and unconnected to the ground line. 
     
     
       5. The semiconductor integrated circuit device of  claim 1 , wherein the dummy metal wiring line is formed to protrude from the ground line, and unconnected to the power supply line. 
     
     
       6. The semiconductor integrated circuit device of  claim 1 , wherein the dummy metal wiring line includes a plurality of small sections. 
     
     
       7. The semiconductor integrated circuit device of  claim 6 , wherein one of the plurality of small sections is connected to the power supply line. 
     
     
       8. The semiconductor integrated circuit device of  claim 6 , wherein one of the plurality of small sections is connected to the ground line. 
     
     
       9. The semiconductor intergrated circuit device of  claim 1 , wherein the first metal wiring line has another portion perpendicular to the dummy metal wiring line. 
     
     
       10. A semiconductor integrated circuit device comprising:
 a power supply line and a ground line each placed to extend in a first direction; and 
 first and second cells place in region interposed between the power supply line and the ground line to be adjacent to each other in the first direction, and each having a transistor and an intra-cell line each for implementing a circuit fuction, wherein 
 a dummy metal wiring line formed on a different layer than a gate of the transistor of the first and second cells and extending in a second direction orthogonal to the first direction is placed in a boundary portion between the first and second cells so as not to short-circuit the power supply line and the ground line, 
 a first metal wiring line in the first cell has a portion parallel with the dummy metal wiring line, the portion being connected with source or drain of a transistor and closest to the boundary portion between the first and second cells amoung the intra-cell line in the first cell, and 
 the first metal wiring line and the dummy metal wiring line are formed in a same wiring layer. 
 
     
     
       11. The semiconductor integrated circuit device of  claim 10 , wherein the dummy metal wiring line is in a floating state which is not connected to either of the power supply line and the ground line. 
     
     
       12. The semiconductor integrated circuit device of  claim 10 , wherein the dummy metal wiring line includes a first line formed to protude from the power supply line, and a second line formed to protude from the ground line, and unconnected to the first line. 
     
     
       13. The semiconductor integrated circuit device of  claim 10 , wherein the dummy metal wiring line is formed to protude from the power supply line, and unconnected to the ground line. 
     
     
       14. The semiconductor integrated circuit device of  claim 10 , wherein the dummy metal wiring line is formed to protrude from the ground line, and unconnected to the power supply line. 
     
     
       15. The semiconductor integrated circuit device of  claim 10 , wherein the dummy metal wiring line includes a plurlity of small sections. 
     
     
       16. The semiconductor integrated circuit device of  claim 15 , wherein one of the plurality of small sections is connected to the power supply line. 
     
     
       17. The semiconductor integrated circuit device of  claim 15 , wherein one of the plurity of small section is connected to the ground line.