No stress level shifter

Abstract

A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

1. A circuit, comprising:
 a plurality of cascaded shifting stages that are configured to shift a voltage of the circuit by a voltage swing; 
 a signal generator that is configured to generate an amplified single level shifted final output signal that has an output voltage level that is higher than an input voltage level, wherein the amplified single level shifted final output signal corresponds to a single binary input signal of a first stage of the cascaded shifting stages and is based on a non-inverted shifted output signal and an inverted shifted output signal of a second stage of the cascaded shifting stages; and 
 a diode circuit that is configured to limit a lower voltage of limited voltage swing output signals of the cascaded shifting stages to a non-zero lower value. 
 
     
     
       2. The circuit of  claim 1 , wherein the first stage is configured to receive the single binary input signal having an input voltage level. 
     
     
       3. The circuit of  claim 2 , wherein the first stage is further configured to generate a non-inverted first-stage limited voltage swing shifted output signal and an inverted first-stage limited voltage swing shifted output signal, and a voltage swing of the limited voltage swing output signals swings between the non-zero lower value and an upper value that is less than or equal to the voltage rating. 
     
     
       4. The circuit of  claim 3 , wherein the second stage is configured to receive the non-inverted first-stage limited voltage swing shifted output signal and the inverted first-stage limited voltage swing shifted output signal. 
     
     
       5. The circuit of  claim 4 , wherein the signal generator is a comparator that is configured to receive the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal and configured to generate the amplified single level shifted final output signal. 
     
     
       6. The circuit of  claim 2 , wherein the first stage is further configured to have a voltage rating that is a maximum source-to-drain voltage rating of a transistor in the first stage. 
     
     
       7. The circuit of  claim 4 , wherein the second stage is further configured to generate a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a voltage swing of the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal swings between a non-zero lower value and an upper value that is less than or equal to the non-zero lower value plus a voltage rating of a transistor in the second stage. 
     
     
       8. The circuit of  claim 1 , wherein the first stage further comprises:
 a leaker circuit that is configured to provide a constant current flow through the diode circuit to maintain an intermediate voltage that is supplied at least to the second stage. 
 
     
     
       9. The circuit of  claim 1 , further comprising:
 a monitoring circuit that is configured to monitor whether the single binary input signal is being received and configured to control the first stage to output a predetermined non-inverted first-stage voltage and a predetermined inverted first-stage voltage. 
 
     
     
       10. The circuit of  claim 9 , wherein the monitoring circuit is further configured to monitor a HIGH voltage source associated with the single binary input signal and configured to determine that the single binary input signal is not being received upon determining that the HIGH voltage source is not being received. 
     
     
       11. The circuit of  claim 1 , wherein the circuit is configured to prevent any transistor in the circuit from being exposed to an over-voltage stress under any operational condition. 
     
     
       12. The circuit of  claim 1 , wherein the second stage comprises a differential level shifter. 
     
     
       13. The circuit of  claim 1 , wherein the first stage, the second stage and the signal generator are constructed using thick-oxide P-type and N-type MOS transistors. 
     
     
       14. The circuit of  claim 1 , wherein the signal generator is further configured to generate a maximum voltage of the amplified single level shifted final output signal that is less than or equal to a non-zero lower value plus a transistor voltage rating defined for a transistor technology used in the circuit. 
     
     
       15. The circuit of  claim 1 , wherein the circuit is constructed from MOS transistors with a source-to-drain voltage rating of 1.8 volts±10%. 
     
     
       16. A method of generating a level shifted signal using a circuit, comprising:
 shifting a voltage of the circuit by a plurality of cascaded shifting stages with a voltage swing; 
 generating an amplified single level shifted final output signal that has an output voltage level that is higher than an input voltage level, wherein the amplified single level shifted final output signal corresponds to a single binary input signal of a first stage of the cascaded shifting stages and is based on a non-inverted shifted output signal and an inverted shifted output signal of a second stage of the cascaded shifting stages; and 
 limiting a lower voltage of limited voltage swing output signals of the cascaded shifting stages to a non-zero lower value by a diode circuit. 
 
     
     
       17. The method of  claim 16 , further comprising:
 generating a voltage swing limited non-inverted first-stage shifted output signal and voltage swing limited inverted first-stage shifted output signal based on the single binary input signal having an input voltage level, wherein a voltage swing of the voltage swing limited first stage shifted output signals swings between a non-zero value and a value that is less than or equal to a voltage rating of a transistor in the circuit generating the first stage shifted output signals. 
 
     
     
       18. The method of  claim 17 , further comprising:
 generating a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal based on the non-inverted first-stage shifted output signal and the inverted first-stage shifted output signal. 
 
     
     
       19. The method of  claim 18 , wherein an intermediate voltage source used to generate the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal is based on source voltages used to generate the first stage shifted output signals. 
     
     
       20. The method of  claim 16 , further comprising:
 generating a predetermined constant non-inverted second-stage shifted output signal and a predetermined constant inverted second-stage shifted output signal in response to detecting that the single binary input signal is not being received.