Transmit data timing control

Abstract

An RF transmitter that, during a transmission session, transmits multiple data slices, which are synchronized to each other by a transmit counter. Typically, the time between transmission of consecutive data slices is constant; however, to synchronize the transmission session with a base station, the time between transmission of consecutive data slices may be occasionally adjusted. By using the transmit counter to synchronize data transmissions, effects of uncompensated latencies or variances in latencies may be reduced or eliminated.

1. A method comprising:
 receiving a transmit control command from a base station, wherein the transmit control command includes one of an advance transmission instruction and a delay transmission instruction; 
 receiving, at a logical NOR gate, a compression mode interrupt signal and a transmit activation signal; 
 outputting, from the logical NOR gate, a reset signal; 
 incrementing a transmit counter based on a count of the transmit counter and the transmit control command, wherein the transmit counter is reset a clock cycle early in response to receipt of the advance transmission instruction, wherein the transmit counter is held in reset for a clock cycle in response to receipt of the delay transmission instruction, and wherein a pulse is provided from a transmit counter output upon resetting; 
 generating a transmit synchronization signal based on outputted pulses from the transmit counter logically anded with a transmit activation signal, wherein the transmit synchronization signal includes a transmit time period; 
 slicing baseband transmit data into a plurality of data slices for transmission; 
 gating each of the plurality of data slices provided to an RF modulator for transmission based on the transmit synchronization signal, wherein one of the plurality of data slices is provided to the RF modulator per the transmit time period; and 
 generating an RF transmit signal with the RF modulator based on each of the plurality of data slices, such that transmission of each of the data slices is synchronized to the base station. 
 
     
     
       2. Radio frequency (RF) circuitry comprising:
 an RF receiver configured to receive a transmit control command from a base station; 
 a transmit counter configured to:
 receive, at a logical NOR gate, a compression mode interrupt signal and a transmit activation signal; 
 output, from the logical NOR gate, a reset signal; 
 receive a transmit counter clock signal; 
 increment a count of the transmit counter based on the transmit counter clock signal, the count of the transmit counter, and the transmit control command,
 wherein response to the transmit control command containing an advance transmission instruction, the transmit counter is reset at least a clock cycle early, 
 wherein response to the transmit control command containing a delay transmission instruction the transmit counter is held in reset for at least a clock cycle, and 
 wherein a pulse is provided from a transmit counter output upon resetting; and 
 
 generate a transmit synchronization signal having a first period and based on outputted pulses from the transmit counter logically anded with a transmit activation signal, such that the first period is based on the count of the transmit counter; and 
 
 an RF transmitter configured to:
 receive baseband transmit data; 
 slice the baseband transmit data into a plurality of data slices; 
 receive the transmit synchronization signal; 
 gate transmission of each of the data slices based upon the transmit synchronization signal; and 
 
 wherein the gated transmission of each of the data slices is synchronized with the base station. 
 
     
     
       3. The RF circuitry of  claim 2  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; and 
 disable the transmit synchronization signal during the inactive state of the transmit activation signal. 
 
     
     
       4. The RF circuitry of  claim 2  wherein the transmit counter is further configured to:
 receive a compressed mode interrupt signal having an interrupted state and a non-interrupted state; and 
 increment during the interrupted state. 
 
     
     
       5. The RF circuitry of  claim 4  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; 
 not increment during a combination of the inactive state of the transmit activation signal and the non-interrupted state of the compressed mode interrupt signal. 
 
     
     
       6. The RF circuitry of  claim 4  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; 
 reset during a combination of the inactive state of the transmit activation signal and the non-interrupted state of the compressed mode interrupt signal. 
 
     
     
       7. The RF circuitry of  claim 2  wherein:
 the transmit counter is further configured to:
 receive a compressed mode interrupt signal having an interrupted state and a non-interrupted state; and 
 increment the count of the transmit counter during the interrupted state of the compressed mode interrupt signal; 
 
 the compressed mode interrupt signal is based on the at least one transmit control command; and 
 decoding circuitry configured to:
 receive transmit control information; 
 provide baseband transmit data; 
 provide the transmit activation signal; and 
 provide the compressed mode interrupt signal. 
 
 
     
     
       8. The RF circuitry of  claim 7  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; and 
 hold the count of the transmit counter during a combination of the inactive state of the transmit activation signal and the non-interrupted state of the compressed mode interrupt signal. 
 
     
     
       9. The RF circuitry of  claim 2  wherein the RF transmitter further comprises a data slice buffer configured to provide each of the plurality of data slices for transmission by an RF modulator based on the transmit synchronization signal. 
     
     
       10. The RF circuitry of  claim 2  wherein:
 the transmit counter clock signal has a plurality of clock cycles, such that each of the plurality of clock cycles has a duration of a second period; 
 transmit timing adjustment information has one of at least a first value and a second value; 
 the first period is approximately equal to a value of the second period times a first integer; and 
 when the transmit timing adjustment information has the first value, the first integer is equal to a nominal value. 
 
     
     
       11. The RF circuitry of  claim 10  wherein when the transmit timing adjustment information has the second value, the first integer is equal to the nominal value minus a second integer. 
     
     
       12. The RF circuitry of  claim 10  wherein when the transmit timing adjustment information has the second value, the first integer is equal to the nominal value plus a second integer. 
     
     
       13. The RF circuitry of  claim 12  wherein the transmit timing adjustment information has one of the first value, the second value, and a third value, such that when the transmit timing adjustment information has the third value, the first integer is equal to the nominal value minus a third integer. 
     
     
       14. The RF circuitry of  claim 13  wherein:
 when the transmit timing adjustment information has the first value, the transmit counter is incremented for each of the plurality of clock cycles; 
 when the transmit timing adjustment information has the second value, the transmit counter is not incremented for each of the plurality of clock cycles; and 
 when the transmit timing adjustment information has the third value, the transmit counter is incremented twice for at least one of the plurality of clock cycles. 
 
     
     
       15. The RF circuitry of  claim 14  wherein the second integer is equal to one and the third integer is equal to one. 
     
     
       16. The RF circuitry of  claim 15  wherein:
 the value of the second period is approximately equal to one divided by 31.2 megahertz; 
 the nominal value is equal to sixty-five; and 
 a nominal duration of the first period is equal to eight times a duration of a chip. 
 
     
     
       17. The RF circuitry of  claim 16  wherein:
 the transmit counter is further configured to:
 receive a compressed mode interrupt signal having an interrupted state and a non-interrupted state; 
 receive a transmit activation signal having an active state and an inactive state; 
 increment during the interrupted state of the compressed mode interrupt signal; and 
 not increment during a combination of the inactive state of the transmit activation signal and the non-interrupted state of the compressed mode interrupt signal; 
 
 a duration of a slot is equal to 2560 times the duration of the chip; and 
 a duration of the non-interrupted state is equal to at least three times the duration of the slot. 
 
     
     
       18. The RF circuitry of  claim 2  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; and 
 reset during the inactive state of the transmit activation signal. 
 
     
     
       19. The RF circuitry of  claim 2  wherein the transmit counter is further configured to:
 receive a transmit activation signal having an active state and an inactive state; and 
 disable the transmit synchronization signal during the inactive state of the transmit activation signal. 
 
     
     
       20. The RF circuitry of  claim 2  wherein the advance transmission instruction includes an advance count period, the transmit counter is reset early by the advance count period of two or more clock cycles. 
     
     
       21. The RF circuitry of  claim 2  wherein the delay transmission instruction includes a delay count period, the transmit counter is held in reset for the delay count period of two or more clock cycles. 
     
     
       22. Radio frequency (RF) circuitry comprising:
 an RF receiver configured to receive an RF input signal from a base station, and to output baseband receive information, wherein the RF input signal includes a transmit control command, and wherein the transmit control command includes at least one of a start command, an adjust command, an interrupt command, and a resume command; 
 a baseband controller configured to receive the baseband receive information from the RF receiver, and to output baseband transmit information, and wherein the baseband receive information includes the transmit control command; 
 decoding circuitry configured to receive the baseband transmit information, and to output: baseband transmit data, a transmit activation signal, a transmit adjustment signal, and a compressed mode interrupt signal; 
 transmit counter circuitry configured to receive: a transmit counter clock signal, the transmit activation signal from the decoding circuitry, the transmit adjustment signal from the decoding circuitry, and the compressed mode interrupt signal from the decoding circuitry, and to output a transmit synchronization signal; and 
 a radio frequency (RF) transmitter configured to receive the transmit synchronization signal from the transmit counter circuitry, to receive the baseband transmit data from the decoding circuitry, and to output a radio frequency (RF) output signal; 
 a logical NOR gate configured to receive the compression mode interrupt signal and the transmit activation signal, and to output a reset signal; 
 a transmit counter configured to receive: the transmit counter clock signal, the transmit adjustment signal, and the reset signal, and to output a transmit counter output signal; 
 a logical AND gate configured to receive the transmit counter output signal and the transmit activation signal, and to output a transmit synchronization signal. 
 
     
     
       23. The RF circuitry of  claim 22 , wherein the transmit counter circuitry is configured to:
 increment an internal count value from zero until a maximum value during a nominal count period while the transmit activation signal is enabled and the reset signal is not enabled; 
 drop the internal count value to zero when the maximum value is reached at the end of the nominal count period; 
 output the transmit counter output signal after dropping the internal count value to zero, wherein the transmit counter output signal is a transmit counter pulse; 
 output the transmit synchronization signal from the logical AND gate upon the logical AND gate receiving the transmit counter pulse and receiving an enabled transmit activation signal, wherein the transmit synchronization signal includes a transmit synchronization pulse, and 
 wherein the transmit synchronization pulse is caused by and corresponds with the transmit counter pulse. 
 
     
     
       24. The RF circuitry of  claim 23 , wherein the transmit counter circuitry is configured to:
 reduce a time period between transmit counter pulses by at least one clock cycle by dropping the internal count value to zero before the maximum count value is reached; and 
 increase the time period between transmit counter pulses by at least one clock cycle by holding the internal count value at zero for at least one clock cycle after the internal count value has dropped to zero. 
 
     
     
       25. The RF circuitry of  claim 24 , wherein the transmit counter circuitry is configured to:
 reduce the time period between transmit counter pulses by at least two clock cycles by dropping the internal count value to zero at least two counts before the maximum count value is reached; and 
 increase the time period between transmit counter pulses by at least two clock cycle by holding the internal count value at zero for at least two clock cycles after the internal count value has dropped to zero.