US8191248B2ActiveUtilityA1

Method for making an embedded structure

66
Assignee: LIU YI-CHUNPriority: Sep 17, 2008Filed: Sep 17, 2008Granted: Jun 5, 2012
Est. expirySep 17, 2028(~2.2 yrs left)· nominal 20-yr term from priority
H05K 3/107H05K 3/0032H05K 3/0055H05K 3/184H05K 3/426H05K 2201/0236H05K 2203/0571H05K 2203/1388Y10T29/49155Y10T29/49117Y10T29/49165Y10T29/49144
66
PatentIndex Score
2
Cited by
14
References
18
Claims

Abstract

An embedded structure of circuit board is provided. The embedded structure of the present invention includes a dielectric layer, a pad opening disposed in the dielectric layer, and a via disposed in the pad opening and in the dielectric layer, wherein the outer surface of the dielectric layer has a substantially even surface.

Claims

exact text as granted — not AI-modified
1. A method for defining an embedded structure, comprising:
 providing a dielectric layer; 
 forming an organic film layer to cover said dielectric layer; 
 forming a via in said dielectric layer and in said organic film layer; 
 performing a cleaning step to roughen an inner wall of said via such that the inner wall of said via has a roughness C; 
 patterning said dielectric layer and said organic film layer to form a pad opening overlapping with said via in said dielectric layer and having a roughness B; and 
 removing said organic film layer to expose an outer surface of said dielectric layer having a roughness A, wherein said via and said pad opening together define said embedded structure and A, B, C are mutually different. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming a trench in said dielectric layer, wherein the inner wall of said trench has said roughness B. 
 
     
     
       3. The method of  claim 1 , wherein C>B>A. 
     
     
       4. The method of  claim 1 , further comprising:
 performing a first deposition step to form a conductive layer filling said via and said pad opening. 
 
     
     
       5. The method of  claim 4 , wherein said first deposition step is an electroless plating. 
     
     
       6. The method of  claim 5 , wherein said dielectric layer acts as a seed layer for said electroless plating. 
     
     
       7. The method of  claim 4 , further comprising:
 performing a second deposition step so that said conductive layer fills said via and said pad opening. 
 
     
     
       8. The method of  claim 1 , wherein said dielectric layer comprises a metallic complex. 
     
     
       9. The method of  claim 8 , wherein said metallic complex comprises a metal selected from a group consisting of Mn, Cr, Pd and Pt. 
     
     
       10. The method of  claim 1 , wherein said organic film layer comprises a hydrophilic polymer, wherein said hydrophilic polymer comprises a functional group selected form a group consisting of hydroxyl group (—OH), amide group (—CONH2), sulfonic group (—SO3H) and carboxylic group (—COOH). 
     
     
       11. The method of  claim 1 , wherein said organic film layer comprises a hydrophobic polymer, wherein said hydrophobic polymer is selected form a group consisting of methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamide resin, and polysiloxane resin. 
     
     
       12. The method of  claim 1 , wherein said cleaning step is selected from a group consisting of plasma and an oxidizing agent. 
     
     
       13. The method of  claim 1 , wherein said patterning said dielectric layer is carried out by laser. 
     
     
       14. The method of  claim 1 , wherein patterning said dielectric layer activates the surface of said dielectric layer. 
     
     
       15. The method of  claim 1 , wherein said roughness C is expressed by 0.5 μm<Ra<5.0 μm. 
     
     
       16. The method of  claim 1 , wherein said roughness B is expressed by 0.2 μm<Ra<0.5 μm. 
     
     
       17. The method of  claim 1 , further comprising:
 removing said organic film layer so as to leave said dielectric layer a substantially even surface. 
 
     
     
       18. The method of  claim 1 , wherein said roughness A is expressed by Ra<0.5μm.

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