Trapping set decoding for transmission frames

Abstract

Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword. A selection processor is coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits.

1. A trapping set decoder comprising:
 a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword; and 
 a selection processor coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits. 
 
     
     
       2. The trapping set decoder of  claim 1  wherein the decoded codeword is a decoded LDPC codeword. 
     
     
       3. The trapping set decoder of  claim 1  wherein the trapping sets of bits are of Order 8. 
     
     
       4. The trapping set decoder of  claim 1  wherein the trapping sets of bits are of Order 10. 
     
     
       5. The trapping set decoder of  claim 1  wherein the statistical measures comprise log likelihood ratios. 
     
     
       6. The trapping set decoder of  claim 5  and further comprising summing circuitry to generate a log likelihood sum of the log likelihood ratios for each of the trapping sets, and wherein the selection of one from a group of trapping sets is based on the sums of the log likelihood ratios of the bits for each of the group of trapping sets. 
     
     
       7. The trapping set decoder of  claim 1  wherein the trapping set decoder is embodied in a 10 GBASE-T receiver circuit. 
     
     
       8. The trapping set decoder of  claim 1  wherein the detector detects a signature that corresponds to the one or more trapping sets of bits. 
     
     
       9. A method for decoding trapping sets, the method comprising:
 receiving a decoded codeword; 
 determining whether at least a portion of the decoded codeword exhibits a trapping set signature; 
 identifying a group of trapping set error patterns corresponding to the trapping set signature; 
 selecting a trapping set error pattern from the identified group of trapping set error patterns based on probability metrics associated with the respective trapping set error patterns. 
 
     
     
       10. The method of  claim 9  wherein the probability metrics comprise log likelihood ratios. 
     
     
       11. The method of  claim 10  wherein the selecting comprises summing a plurality of the log likelihood ratios for at least a plurality of the bits in each identified trapping set. 
     
     
       12. The method of  claim 9  and further comprising correcting bits in the received codeword based on the selected trapping set. 
     
     
       13. The method of  claim 9  wherein receiving comprises receiving an LDPC decoded codeword. 
     
     
       14. A receiver circuit comprising:
 an LDPC decoder; and 
 a trapping set decoder including
 a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword and 
 a selection processor coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits. 
 
 
     
     
       15. The receiver circuit of  claim 14  wherein the receiver circuit is embodied in an ethernet transceiver. 
     
     
       16. The receiver circuit of  claim 15  wherein the ethernet transceiver comprises a 10 GBASE-T ethernet transceiver.