Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode

Abstract

An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

1. An apparatus for clock and voltage scaling on an interface, the apparatus comprising:
 a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface; 
 a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature; and 
 a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency. 
 
     
     
       2. The apparatus of  claim 1 , wherein the interface includes a memory controller. 
     
     
       3. The apparatus of  claim 1  further comprising:
 a plurality of the plurality of controlled delay line elements each coupled to the delay-locked loop and each arranged to use the unique code to build the delay and generate an appropriate respective delayed data strobe. 
 
     
     
       4. The apparatus of  claim 1 , wherein the interface is arranged to switch between one of the controlled delay line elements and a chain of more than one of the controlled delay line elements based on a handshake protocol with the device power manager when there is no on-going access on a second interface. 
     
     
       5. The apparatus of  claim 1 , wherein the substantially constant fixed frequency clock and the scalable frequency clock are derived from the same clock source. 
     
     
       6. The apparatus of  claim 1 , wherein the substantially constant fixed frequency clock and the scalable frequency clock are not balanced. 
     
     
       7. The apparatus of  claim 1 , wherein the up to N controlled delay line elements are chained together by at least one multiplexer. 
     
     
       8. The apparatus of  claim 1 , wherein the scalable frequency clock that scales the frequency supplied to the interface may be changed. 
     
     
       9. The apparatus of  claim 1 , wherein the interface is a double data rate interface. 
     
     
       10. The apparatus of  claim 1 , wherein the substantially constant fixed frequency clock and the scalable frequency clock are separate. 
     
     
       11. The apparatus of  claim 1 , wherein the unique code remains substantially stable for at least one of the process, the voltage, and the temperature when the scalable frequency clock scales the frequency. 
     
     
       12. A system for clock and voltage scaling on an interface and for providing a digital phase lock loop high speed bypass mode, the system comprising:
 a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface; and 
 a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature. 
 
     
     
       13. The system of  claim 12 , further comprising:
 a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency. 
 
     
     
       14. The system of  claim 13 , further comprising:
 a first digital phase lock loop in a first clock domain having a high speed clock; and 
 at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input, wherein the device power manager is arranged to control the first output of the first glitchless multiplexer according to preselected settings and is synchronized locally to ensure proper switching. 
 
     
     
       15. The system of  claim 14 , further comprising:
 a control logic element of the at least one second digital phase lock loop arranged to control a second output of the second glitchless multiplexer, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.