Apparatus and method for data strobe and timing variation detection of an SDRAM interface

Abstract

An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

1. An apparatus for data strobe and timing variation detection of an SDRAM interface, comprising:
 a differential-signal to single-end signal converter connected to a synchronous transmission interface for receiving a pair of differential data strobe signals and converting the differential data strobe signal into a single-end data strobe signal; 
 a first phase delay circuit connected to the differential-signal to single-end signal converter for regulating the single-end data strobe signal to produce a delayed single-end data strobe signal; 
 a data latch circuit connected to the phase delay circuit for latching synchronous data from the synchronous transmission interface by the delayed single-end data strobe signal; and 
 a timing variation detector for detecting and calibrating a variation amount between a timing of the synchronous transmission interface and an internal timing of a memory controller chip. 
 
     
     
       2. The apparatus as claimed in  claim 1 , wherein the first phase delay circuit has a phase delay ranging from zero to 180 degrees. 
     
     
       3. The apparatus as claimed in  claim 1 , wherein the timing variation detector comprises a second phase delay circuit to produce an early clock strobe signal for detecting an early timing variation event present in the delayed single-end data strobe signal. 
     
     
       4. The apparatus as claimed in  claim 1 , wherein the timing variation detector comprises a second phase delay circuit to produce a late clock strobe signal for detecting a late timing variation event present in the delayed single-end data strobe signal because of the first phase delay circuit. 
     
     
       5. The apparatus as claimed in  claim 1 , wherein the data latch circuit comprises 2N First-In-First-Out buffers to temporarily store data sent by the synchronous transmission interface, where N is a positive integer. 
     
     
       6. The apparatus as claimed in  claim 1 , wherein the synchronous transmission interface is a double data rate (DDR) SDRAM transmission interface. 
     
     
       7. An SDRAM system, comprising:
 a DDR 2/3 SDRAM for temporarily storing data; and 
 a memory controller connected to the DDR 2/3 SDRAM for accessing data, the memory controller including: 
 a differential-signal to single-end signal converter connected to a transmission interface for receiving a pair of differential data strobe signals outputted by the transmission interface and converting the differential data strobe signal into a single-end data strobe signal; 
 a first phase delay circuit connected to the differential-signal to single-end signal converter for regulating the single-end data strobe signal to produce a delayed single-end data strobe signal; 
 a data latch circuit connected to the phase delay circuit for latching synchronous data from the transmission interface according to the delayed single-end data strobe signal; and 
 a timing variation detector for detecting and calibrating a variation amount between a timing of the synchronous transmission interface and an internal timing of a memory controller chip. 
 
     
     
       8. The system as claimed in  claim 7 , wherein the first phase delay circuit has a phase delay ranging from zero to 180 degrees. 
     
     
       9. The system as claimed in  claim 7 , wherein the timing variation detector comprises a second phase delay circuit to produce an early clock strobe signal to thereby detect an early timing variation event present in the delayed single-end data strobe signal. 
     
     
       10. The system as claimed in  claim 7 , wherein the timing variation detector comprises a second phase delay circuit to produce a late clock strobe signal for detecting a late timing variation event present in the delayed single-end data strobe signal. 
     
     
       11. The system as claimed in  claim 7 , wherein the data latch circuit comprises 2N First-In-First-Out buffers to temporarily store data sent by the synchronous transmission interface, where N is a positive integer. 
     
     
       12. The system as claimed in  claim 7 , wherein a delay locked loop of the DDR 2/3 SDRAM is disabled when an operation speed of the DDR 2/3 SDRAM is too low. 
     
     
       13. A method for data strobe and timing variation detection of an SDRAM interface, comprising the steps of:
 (A) converting a pair of differential data strobe signals outputted into a single-end data strobe signal; 
 (B) regulating the single-end data strobe signal to produce a delayed single-end data strobe signal; 
 (C) latching synchronous data from the synchronous transmission interface according to the delayed single-end data strobe signal; and 
 (D) detecting and calibrating a timing variation amount on the synchronous transmission interface and the internal timing of a memory controller chip. 
 
     
     
       14. The method as claimed in  claim 13 , wherein a phase delay of zero to 180 degrees is performed in the step (B). 
     
     
       15. The method as claimed in  claim 13 , wherein the step (D) further comprises a step of:
 (D1) producing an early clock strobe signal to detect an early timing variation event present in the delayed single-end data strobe signal. 
 
     
     
       16. The method as claimed in  claim 13 , wherein the step (D) further comprises a step of:
 (D2) producing a late clock strobe signal based on a second estimated delay value to detect a late timing variation event present in the delayed single-end data strobe signal. 
 
     
     
       17. The method as claimed in  claim 13 , wherein the synchronous transmission interface is a DDR 2/3/4 SDRAM transmission interface.