Latency counter, semiconductor memory device including the same, and data processing system

Abstract

A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.

1. A latency counter that counts a latency of an internal command, the latency counter comprising:
 a counter circuit that counts a clock signal; and 
 a point-shift FIFO circuit, wherein 
 the point-shift FIFO circuit includes: 
 a plurality of first latch circuits that latch the internal command; 
 an input selecting circuit that supplies the internal command to one of a plurality of signal paths based on a count value of the counter circuit; 
 a shift circuit that supplies the internal command on one of the signal paths to a predetermined one of the first latch circuits based on a preset correspondence relation between the signal paths and the first latch circuits; and 
 an output selecting circuit that outputs the internal command stored in one of the first latch circuits based on the count value of the counter circuit, wherein 
 the input selecting circuit includes a plurality of timing control circuits, each of the timing control circuits being allocated to an associated one of the signal paths, and 
 each of the timing control circuits includes: 
 a second latch circuit that latches the internal command; and 
 a first gate circuit that outputs the internal command stored in the second latch circuit to an associated one of the signal paths in response to activation of a corresponding count value of the counter circuit, and wherein 
 each of the second latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to deactivation of the corresponding count value of the counter circuit. 
 
     
     
       2. The latency counter as claimed in  claim 1 , wherein each of the first latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to activation of a different count value of the counter circuit from the corresponding count value. 
     
     
       3. The latency counter as claimed in  claim 2 , wherein each of the first latch circuits is reset in response to activation of a count value that is subsequent to the corresponding count value. 
     
     
       4. The latency counter as claimed in  claim 1 , wherein
 the internal command is generated in n cycles of the clock signal at shortest, 
 the first latch circuits are divided into n groups, 
 outputs of the first latch circuits belonging to a same group are wired-ORed, and 
 the output selecting circuit selects one of the first latch circuits belonging to a group different from a current group each time the count value is updated. 
 
     
     
       5. The latency counter as claimed in  claim 4 , wherein the point-shift FIFO circuit further includes:
 a second gate circuit that combines outputs of the n groups; and 
 a third gate circuit that shortens an activation period of the internal command output from the second gate circuit by 1/n. 
 
     
     
       6. The latency counter as claimed in  claim 1 , wherein the counter circuit includes:
 a dividing circuit that generates, based on the clock signal, a plurality of divided clocks that include at least a first divided clock and a second divided clock having mutually different phases; 
 a first counter unit that counts the first divided clock; 
 a second counter unit that takes in a count value of the first counter unit in synchronization with the second divided clock; and 
 a selecting circuit that exclusively selects the count value of the first and second counter units. 
 
     
     
       7. The latency counter as claimed in  claim 6 , wherein the selecting circuit selects the count value of the first counter unit based on the first divided clock and selects the count value of the second counter unit based on the second divided clock. 
     
     
       8. The latency counter as claimed in  claim 6 , wherein the first counter unit includes a ripple counter that outputs a count value in a binary format. 
     
     
       9. The latency counter as claimed in  claim 8 , wherein the first counter unit includes a first delay circuit that matches a change timing of a plurality of bits that constitute the count value. 
     
     
       10. The latency counter as claimed in  claim 6 , wherein the second counter unit includes a second delay circuit that delays the second divided clock, and takes in the count value of the first counter unit in response to the second divided clock that is delayed by the second delay circuit. 
     
     
       11. The latency counter as claimed in  claim 10 , wherein an amount of delay of the second delay circuit is larger than an amount of delay of the first delay circuit. 
     
     
       12. The latency counter as claimed in  claim 1 , wherein the shift circuit can change the correspondence relation between the signal paths and the first latch circuits based on a setting signal. 
     
     
       13. The latency counter as claimed in  claim 1 , further comprising a mode switching circuit that supplies the internal command to the point-shift FIFO circuit relatively early in a first operation mode and supplies the internal command to the point-shift FIFO circuit relatively late in a second operation mode. 
     
     
       14. The latency counter as claimed in  claim 13 , wherein the first operation mode is a state where the clock signal is phase-controlled and the second operation mode is a state where the clock signal is not phase-controlled. 
     
     
       15. A semiconductor memory device comprising a latency counter that counts a latency of an internal command, wherein
 the latency counter comprises: 
 a counter circuit that counts a clock signal; and 
 a point-shift FIFO circuit, wherein 
 the point-shift FIFO circuit includes: 
 a plurality of first latch circuits that latch the internal command; 
 an input selecting circuit that supplies the internal command to one of a plurality of signal paths based on a count value of the counter circuit; 
 a shift circuit that supplies the internal command on one of the signal paths to a predetermined one of the first latch circuits based on a preset correspondence relation between the signal paths and the first latch circuits; and 
 an output selecting circuit that outputs the internal command stored in one of the first latch circuits based on the count value of the counter circuit, wherein 
 the input selecting circuit includes a plurality of timing control circuits, each of the timing control circuits being allocated to an associated one of the signal paths, and 
 each of the timing control circuits includes: 
 a second latch circuit that latches the internal command; and 
 a first gate circuit that outputs the internal command stored in the second latch circuit to an associated one of the signal paths in response to activation of a corresponding count value of the counter circuit, and wherein 
 each of the second latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to deactivation of the corresponding count value of the counter circuit. 
 
     
     
       16. A data processing system comprising:
 a semiconductor memory device; and 
 a data processor connected to the semiconductor memory device via a system bus, wherein 
 the semiconductor memory device comprises a latency counter that counts a latency of an internal command, wherein 
 the latency counter comprises a counter circuit that counts a clock signal and a point-shift FIFO circuit, wherein 
 the point-shift FIFO circuit includes: 
 a plurality of first latch circuits that latch the internal command; 
 an input selecting circuit that supplies the internal command to one of a plurality of signal paths based on a count value of the counter circuit; 
 a shift circuit that supplies the internal command on one of the signal paths to a predetermined one of the first latch circuits based on a preset correspondence relation between the signal paths and the first latch circuits; and 
 an output selecting circuit that outputs the internal command stored in one of the first latch circuits based on the count value of the counter circuit, wherein 
 the input selecting circuit includes a plurality of timing control circuits, each of the timing control circuits being allocated to an associated one of the signal paths, and 
 each of the timing control circuits includes: 
 a second latch circuit that latches the internal command; and 
 a first gate circuit that outputs the internal command stored in the second latch circuit to an associated one of the signal paths in response to activation of a corresponding count value of the counter circuit, and wherein 
 each of the second latch circuits is an SR latch circuit that is set in response to activation of the internal command and is reset in response to deactivation of the corresponding count value of the counter circuit.