Semiconductor integrated circuit having level regulation for reference voltage

Abstract

A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

1. A semiconductor integrated circuit, comprising:
 a reference voltage pad that is configured to receive an external reference voltage; 
 an internal reference voltage generator that is configured to generate a plurality of internal reference voltages by dividing a voltage in response to a voltage change signal; 
 a trimming block that is configured to output one of the plurality of internal reference voltages as a reference voltage; and 
 a reference voltage supply unit that is configured to output the external reference voltage as the reference voltage if the voltage change signal is disabled, and cuts off output of the external reference voltage if the voltage change signal is enabled. 
 
     
     
       2. The semiconductor integrated circuit of  claim 1 , further comprising:
 a plurality of input buffers that buffer data by using the reference voltage output from the trimming block or the reference voltage output from the reference voltage supply unit. 
 
     
     
       3. The semiconductor integrated circuit of  claim 1 , wherein enabling of the voltage change signal is determined according to whether or not the reference voltage is generated, using the external reference voltage and the internal reference voltage, and wherein the voltage change signal is a signal generated according to whether or not a fuse is short-circuited, a signal from an MRS, or a signal received from the outside of the semiconductor integrated circuit. 
     
     
       4. The semiconductor integrated circuit of  claim 1 , wherein the trimming block is configured to, if a test mode signal is enabled, perform counting and decoding, by using a count enable signal, and to select and output one from among the plurality of internal reference voltages, and if the test mode signal is disabled, to select and output. One from among the plurality of internal reference voltages in response to a plurality of selection signals. 
     
     
       5. The semiconductor integrated circuit of  claim 4 , wherein the plurality of selection signals are signals generated according to whether or not fuses are short-circuited, signals from an MRS, or signals received from the outside of the semiconductor integrated circuit. 
     
     
       6. The semiconductor integrated circuit of  claim 5 , wherein the trimming block includes:
 a counter that is configured to perform counting in response to the count enable signal and generate a plurality of count signals; 
 a decoder that is configured to decode the plurality of count signals and generate a plurality of decoded signals; 
 a multiplexer unit that is configured to selectively pass the plurality of decoded signals or the plurality of selection signals in response to the test mode signal; and 
 a switching unit that is configured to output one internal reference voltage from among the plurality of internal reference voltages in response to a plurality of signals output from the multiplexer unit. 
 
     
     
       7. A semiconductor integrated circuit, comprising:
 a reference voltage pad that is configured to receive an external reference voltage; 
 a common node to which a reference voltage is applied; 
 an internal reference voltage generator that is configured to generate a plurality of internal reference voltages by voltage dividing in response to a voltage change signal; 
 a trimming block that is configured to supply one of the plurality of internal reference voltages to the common node; and 
 a reference voltage supply unit that is configured to shift down the level of the external reference voltage and supply the level-shifted external reference voltage to the common node, 
 wherein the voltage change signal is enabled according to which of the external reference voltage and the internal reference voltage is used to generate the reference voltage. 
 
     
     
       8. The semiconductor integrated circuit of  claim 7 , wherein the voltage change signal is implemented with a signal generated according to whether or not a fuse is short-circuited, a signal from an MRS, or a signal received from the outside of the semiconductor integrated circuit. 
     
     
       9. The semiconductor integrated circuit of  claim 7 , wherein the trimming block is configured to, if a test mode signal is enabled, perform counting and decoding by using a count enable signal, and to transmit one from among the plurality of internal reference voltages to the common node, and if the test mode signal is disabled, to transmit one from among the plurality of internal reference voltages to the common node in response to a plurality of selection signals. 
     
     
       10. The semiconductor integrated circuit of  claim 9 , wherein the plurality of selection signals are implemented with signals generated according to whether or not fuses are short-circuited, signals from an MRS, or signals received from the outside of the semiconductor integrated circuit. 
     
     
       11. The semiconductor integrated circuit of  claim 10 , wherein the trimming block includes:
 a counter that is configured to perform counting in response to the count enable signal and generates a plurality of count signals; 
 a decoder that is configured to decode the plurality of count signals and generates a plurality of decoded signals; 
 a multiplexer unit that is configured to selectively pass the plurality of decoded signals or the plurality of selection signals in response to the test mode signal; and 
 a switching unit that is configured to transmit one internal reference voltage from among the plurality of internal reference voltages to the common node in response to a plurality of signals output from the multiplexer unit. 
 
     
     
       12. The semiconductor integrated circuit of  claim 10 , further comprising:
 a plurality of input buffers that receive the voltage applied to the common node as the reference voltage and buffer data by using the voltage.