US8217819B2ActiveUtilityPatentIndex 62
Multiplying DAC and a method thereof
Est. expiryNov 8, 2030(~4.4 yrs left)· nominal 20-yr term from priority
H03M 1/0653H03M 1/806
62
PatentIndex Score
3
Cited by
4
References
16
Claims
Abstract
The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
Claims
exact text as granted — not AI-modified1. A multiplying digital-to-analog converter (MDAC), comprising:
an amplifier having an inverting input node, a non-inverting input node and an output node providing an output signal;
a plurality of capacitors, first ends of the plurality of capacitors being electrically coupled to the inverting input node, wherein two of the plurality of capacitors are alternatively configured as a feedback capacitor across the inverting input node and the output node, wherein each of the plurality of capacitors is composed of at least two sub-capacitors;
a plurality of sampling switches, through which second ends of the plurality of capacitors are electrically coupled to an input signal, wherein the plurality of sampling switches are closed during a sampling period;
a plurality of amplifying switches, through which the second ends of the plurality of capacitors are electrically coupled to a plurality of DAC voltages respectively; and
a sorting circuit configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
2. The MDAC of claim 1 , wherein the plurality of amplifying switches comprise:
at least one entire amplifying switch that is closed during an entire amplifying period;
at least one first-phase amplifying switch that is closed during a first-phase amplifying period; and
at least one second-phase amplifying switch that is closed during a second-phase amplifying period, which is mutually exclusive with the first-phase amplifying period.
3. The MDAC of claim 2 , wherein said two capacitors are alternatively configured as the feedback capacitor during the first-phase amplifying period and the second-phase amplifying period respectively.
4. The MDAC of claim 1 , further comprising a sub-analog-to-digital converter (sub-ADC) that receives the input signal and generates a result, based on which the DAC voltages are thus configured.
5. The MDAC of claim 1 , wherein the sub-capacitor with a largest capacitor value is paired with the sub-capacitor with a smallest capacitor value, and the sub-capacitor with a next largest capacitor value is paired with the sub-capacitor with a next smallest capacitor value.
6. The MDAC of claim 1 , wherein the paired capacitors are second sorted, and the second sorted capacitors with a largest capacitor value and a smallest capacitor value are configured as the feedback capacitor.
7. The MDAC of claim 1 , wherein the sorting circuit comprises:
a sorting amplifier having an inverting input node configured to electrically couple first ends of the sub-capacitors, wherein one of the sub-capacitors is selected as a basis sub-capacitor;
a plurality of first switches, through which the basis sub-capacitor samples a reference voltage and the other sub-capacitors are reset during a first period; and
a plurality of second switches, through which the basis sub-capacitor is configured as a feedback capacitor and second ends of the other sub-capacitors are electrically coupled to a plurality of test signals respectively during a second period, which is mutually exclusive with the first period.
8. The MDAC of claim 7 , further comprising a digital controller configured to receive digital codes corresponding to the sub-capacitors from an output node of the sorting amplifier, and then perform sorting on the digital codes.
9. The MDAC of claim 1 , wherein the sub-capacitors comprise eight sub-capacitors, and each said capacitor is composed of two said sub-capacitors, wherein the MDAC is adaptable to a 2.5-bit/stage pipelined ADC.
10. The MDAC of claim 9 , wherein a transfer curve between the output signal and the input signal has seven segments 1-7, and the plurality of DAC voltages comprise three DAC voltages V r1 , V r2 and V r3 , which are arranged as follows:
Segment
1
2
3
4
5
6
7
V r1
V ref
V ref
V ref
0
−V ref
−V ref
−V ref
V r2
V ref
V ref
0
0
0
−V ref
−V ref
V r3
V ref
0
0
0
0
0
−V ref
Total
3V ref
2V ref
V ref
0
−V ref
−2V ref
−3V ref
wherein V ref is a reference voltage of the pipelined ADC.
11. A digital-to-analog conversion method, comprising:
providing a plurality of sub-capacitors;
first sorting the plurality of sub-capacitors, thereby resulting in a plurality of first sorted sub-capacitors;
pairing at least any two of the first sorted sub-capacitors in a manner such that variance of mismatch among the sub-capacitors is averaged, thereby resulting in a plurality of paired capacitors;
second sorting the pair capacitors, thereby resulting in a plurality of second sorted capacitors, wherein the second sorted capacitors with a smallest capacitor value and a largest capacitor value are assigned as a first and a second feedback capacitors of an amplifier during a first-phase amplifying period and a second-phase amplifying period respectively, wherein the first-phase amplifying period and the second-phase amplifying period are mutually exclusive and constitute an entire amplifying period;
in a sampling period, sampling an input signal by the plurality of second sorted capacitors;
in the entire amplifying period, electrically coupling the first and the second feedback capacitors to receive a first one of a plurality of DAC voltages when the first or the second feedback capacitor does not act as the feedback capacitor; and
in the entire amplifying period, electrically coupling the second sorted capacitors excluding the first and the second feedback capacitors to receive the DAC voltages excluding the first DAC voltage respectively.
12. The method of claim 11 , wherein the sub-capacitor with a largest capacitor value is paired with the sub-capacitor with a smallest capacitor value, and the sub-capacitor with a next largest capacitor value is paired with the sub-capacitor with a next smallest capacitor value.
13. The method of claim 11 , further comprising:
performing sub-analog-to-digital conversion on the input signal and generating a result, based on which the DAC voltages are thus configured.
14. The method of claim 11 , wherein the first sorting step comprises:
in a first period, sampling a reference voltage by a first one of the sub-capacitors, while resetting others of the sub-capacitors; and
in a second period that is mutually exclusively with the first period, configuring the first sub-capacitor as a feedback sub-capacitor, while coupling the sub-capacitors excluding the first sub-capacitor to corresponding test signals, thereby obtaining corresponding digital codes sequentially.
15. The method of claim 11 , the sub-capacitors comprise eight sub-capacitors, and each said capacitor is composed of two said sub-capacitors, wherein the method is adaptable to a 2.5-bit/stage pipelined ADC.
16. The method of claim 15 , wherein a transfer curve between an output signal and the input signal has seven segments 1-7, and the plurality of DAC voltages comprise three DAC voltages V r1 , V r2 and V r3 , which are arranged as follows:
Segment
1
2
3
4
5
6
7
V r1
V ref
V ref
V ref
0
−V ref
−V ref
−V ref
V r2
V ref
V ref
0
0
0
−V ref
−V ref
V r3
V ref
0
0
0
0
0
−V ref
Total
3V ref
2V ref
V ref
0
−V ref
−2V ref
−3V ref
wherein V ref is a reference voltage of the pipelined ADC.Cited by (0)
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