US8222106B2ActiveUtilityA1

Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device

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Assignee: HAZAMA HIROAKIPriority: Apr 21, 2009Filed: Dec 1, 2011Granted: Jul 17, 2012
Est. expiryApr 21, 2029(~2.8 yrs left)· nominal 20-yr term from priority
Inventors:Hiroaki Hazama
G11C 16/0483G11C 11/5628H10B 41/30H10B 41/10H10B 41/42H10B 41/40
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Claims

Abstract

A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Claims

exact text as granted — not AI-modified
1. A method of fabricating a nonvolatile semiconductor memory device, comprising:
 forming a gate insulating film on portions of a semiconductor substrate corresponding to first and second cell array regions respectively; 
 forming a charge storage layer on the gate insulating film of the first and second cell array regions; 
 forming a plurality of element isolation trenches so as to extend through the charge storage layer and the gate insulating film and into the semiconductor substrate; 
 forming an element isolation insulating film in the element isolation trenches of each of the first and second cell array regions; 
 etching an upper part of the element isolation insulating film so that the heights of upper surfaces of first and second element isolation insulating films are lower than the height of the charge storage layer and so that the first element isolation insulating film in the first cell array region has an upper surface located higher than an upper surface of the second element isolation insulating film in the second cell array region; 
 forming an interelectrode insulating film on the charge storage layer and the element isolation insulating film; and 
 forming a control electrode on the interelectrode insulating film. 
 
     
     
       2. The method according to  claim 1 , wherein in forming the element isolation insulating film, an equivalent processing is executed in both first and second cell array regions, and in etching the upper part of the element isolation insulating film, the element isolation insulating film is processed so as to have different levels between the first and second cell array regions. 
     
     
       3. The method according to  claim 2 , wherein etching the upper part of the element isolation insulating film includes a first processing in which the element isolation insulating film is processed in both first and second cell array regions so that the necessary level of the first element isolation insulating film is obtained in the first cell array region and a second processing in which after the first processing, the second element isolation insulating film in the second cell array region is processed so as to have the necessary height thereof. 
     
     
       4. The method according to  claim 1 , wherein:
 the nonvolatile semiconductor memory device includes a dummy cell array region located in a boundary between the first and second cell array regions; 
 in forming the gate insulating film on the semiconductor substrate, the gate insulating film is formed in the first and second cell array regions and in the dummy cell array region; and 
 in etching the upper part of the element isolation insulating film, the dummy cell array region is processed so that a boundary between the first and second element isolation insulating films is located in the dummy cell array region.

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